MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1155
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MPC8544COMEDEV
Manufacturer Part Number
MPC8544COMEDEV
Description
KIT DEV EXPRESS MPC8544COM
Manufacturer
Freescale Semiconductor
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544COMEDEV
Contents
Board
For Use With/related Products
MPC8544
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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18.4.1.3
In general, transactions are serviced in the order that they are received. However, transactions can be
reordered as they are sent due to a stalled condition such as a full internal buffer. The following are the
ordering rules for sending the next outstanding request:
18.4.1.4
A PCI Express memory transaction can address a 32- or 64-bit memory space. The Fmt[0] field in the PCI
Express TLP header for a 32-bit address packet is 0; a 64-bit address packet has a Fmt[0] = 1. The PCI
Express TLP header for a memory read transaction has Type[4:0] = 00000 and Fmt[1] = 0. A memory
write transaction has Type[4:0] = 00000 and Fmt[1] = 1. As an initiator, the controller is capable of
sending 32- or 64-bit memory packets. Any transaction from the internal platform that (after passing
through the translation mechanism) has a translated address greater than 4G is sent as a 64-bit memory
packet. Otherwise, a 32-bit memory packet is sent. As a target device, the controller is capable of decoding
32- or 64-bit memory packets. This is done through two 32-bit inbound windows and two 64-bit inbound
windows. All inbound addresses are translated to 36-bit internal platform addresses.
18.4.1.5
The controller does not support I/O transactions as a target. As an initiator, the controller can send I/O
transactions in RC mode only. This can be done by programming one of the outbound translation window’s
attribute to send I/O transactions. All I/O transactions only access 32-bit address I/O space. The PCI
Express TLP header for an I/O read transaction has Type[4:0] = 00010 and Fmt[1] = 0. The PCI Express
TLP header for an I/O write transaction has Type[4:0] = 00010 and Fmt[1] = 1.
Freescale Semiconductor
•
•
•
A posted request can and will bypass all other transactions except another posted request.
A completion can and will only bypass non-posted. It can and will bypass posted requests only if
the relaxed ordering (RO) bit is set.
A non-posted request cannot bypass posted or other non-posted requests, but it can bypass a
completion if the relaxed ordering (RO) bit is set.
PCI Express Configuration Space
Transaction Ordering Rules
Memory Space Addressing
I/O Space Addressing
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PEX_CONFIG_DATA
Figure 18-129. PEX_CONFIG_DATA Byte Ordering
Byte0
Byte3
MSB
Byte1
Byte2
Byte2
Byte1
PCI Express Interface Controller
Byte3
Byte0
LSB
18-101
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