MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1174

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
19.4.1.4
Shown in
Section 4.4.3.11, “eTSEC1 width,” Section 4.4.3.12, “eTSEC3 Width,” and Section 4.4.3.19, “PCI
Arbiter Configuration.”
Table 19-7
19-8
Offset 0xE_000C
Reset
Reset
Bits
6–7
8–9
0
1
2
3
4
5
W
W
R
R PCI_SPD
SGMII1_DIS eTSEC1 in SGMII mode disabled
SGMII3_DIS eTSEC3 SGMII mode disabled
ECW1
ECW1
ECW2
Figure
Name
ECP1
16
n
0
0
describes the bit settings of PORDEVSR.
—
—
—
POR Device Status Register (PORDEVSR)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
19-4, PORDEVSR reports other POR settings for I/O devices as described in
ECW2
eTSEC1 controller width (See
0 Reduced interfaces for eTSEC1(RGMII, RTBI, or 8-bit FIFO on eTSEC1)
1 Full interfaces for eTSEC1(MII, GMII, or TBI on eTSEC1)
eTSEC3 controller width (See
0 Reduced interfaces for eTSEC3 (RGMII, RTBI)
1 Full interface for eTSEC3 (MII, GMII, TBI)
note: FIFO mode on eTSEC3 is always 8-bits regardless of ECW2.
0 eTSEC1 in SGMII mode and if IO_SEL = 001, 011, 101, or 111
1 eTSEC1 in parallel mode
Reserved
0 eTSEC3 in SGMII mode and if IO_SEL = 001, 011, 101, or 111
1 eTSEC3 in parallel mode
Reserved
eTSEC1 controller protocol (See
00 The eTSEC1 controller operates using the 8-bit FIFO if configured in reduced mode.
01 The eTSEC1 controller operates using the MII protocol (or RMII if configured in reduced mode).
10 The eTSEC1 controller operates using the GMII protocol (or RGMII if configured in reduced mode).
11 The eTSEC1 controller operates using the TBI protocol (or RTBI if configured in reduced mode).
Reserved
17
1
n
0
Figure 19-4. POR Device Status Register (PORDEVSR)
SGMII1_
DIS
0
0
2
Table 19-7. PORDEVSR Field Descriptions
19
0
0
3
SGMII3
_DIS
20
0
n
4
ECP3
Section 4.4.3.11, “eTSEC1
Section 4.4.3.12, “eTSEC3
21
Section 4.4.3.13, “eTSEC1
0
n
5
22
n
0
6
ECP1
7
n
—
0
Description
24
0
0
8
RTYPE
25
0
n
9
width.”)
Width.”)
10
26
n
n
Protocol.”)
27
n
0
IO_SEL
12
n
0
Freescale Semiconductor
—
13
Access: Read Only
0
0
PCI_ARB
14
n
0
15
31
0
0