MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 209

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This two-level structure is shown in
Level-1 MMUs have the following features:
The level-2 MMU has the following features:
Freescale Semiconductor
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Four-entry, fully associative TLB array that supports all nine page sizes
64-entry, 4-way set-associative TLB 4-Kbyte array that supports 4-Kbyte pages only
Hardware partially managed by L2 MMU
Supports snooping of TLBs by both internal and external tlbivax instructions
A 16-entry, fully associative L2 TLB array (TLB1) that supports all nine variable page sizes
TLB array (TLB0) that supports only 4-Kbyte pages, as follows:
— e500v1—256-entry, 2-way set-associative TLB array
— e500v2—512-entry, 4-way set-associative TLB array
Hardware assist for TLB miss exceptions
Software managed by tlbre, tlbwe, tlbsx, tlbsync, tlbivax, and mtspr instructions
Supports snooping of TLB by both internal and external tlbivax instructions
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
To instruction unit
To load/store unit
Registers
MAS
Figure
D-L1VSP
TLB Array
I-L1VSP
4-Entry
16-Entry
4-Entry
(TLB1)
L1 Instruction MMU
32-Kbyte D-Cache
32-Kbyte I-Cache
Figure 5-8. MMU Structure
Memory Unit
L1 Data MMU
L2 MMUs
Unified
5-8.
Tags
Tags
256/512-Entry
D-L1TLB4K
I-L1TLB4K
64-Entry
64-Entry
TLB Array
(TLB0)
Core Interface
Data Line
FIll Buffer
Instruction Line
FIll Buffer
Core Complex Overview
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