MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 386

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

DDR Memory Controller

Note that in the absence of refresh support, system software must preserve DDR SDRAM data (such as by

copying the data to disk) before entering the power-saving mode.

The dynamic power-saving mode uses the CKE DDR SDRAM pin to dynamically power down when there

is no system memory activity. The CKE pin is negated when both of the following conditions are met:

CKE is reasserted when a new access or refresh is scheduled or the dynamic power mode is disabled. This

mode is controlled with DDR_SDRAM_CFG[DYN_PWR_MGMT].

Dynamic power management mode offers tight control of the memory system’s power consumption by

trading power for performance through the use of CKE. Powering up the DDR SDRAM when a new

memory reference is scheduled causes an access latency penalty, depending on whether active or precharge

powerdown is used, along with the settings of TIMING_CFG_0[ACT_PD_EXIT] and

TIMING_CFG_0[PRE_PD_EXIT]. A penalty of 1 cycle is shown in

No memory refreshes are scheduled

No memory accesses are scheduled

summarizes the refresh types available in each power-saving mode.

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Table 9-48. DDR SDRAM Power-Saving Modes Refresh Configuration

Figure 9-46. DDR SDRAM Power-Down Mode

Power Saving Mode

Refresh Type

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