MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 727

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Figure 14-86

length of the synchronization cycle depends on the relative start of the synchronization process and varies

with every access. It can vary in length from one to n (clock ratio) local bus clocks.

The second column (compensation cycle) of

of LUPWAIT to get in lockstep with the DSI clock. For example, if the clock divider ratio is 1:3 and the

LUPWAIT reaction time is two local bus clocks, because LUPWAIT is synchronized, then one local bus

clock should be inserted.

Freescale Semiconductor

shows an example for a synchronization mechanism for a clock divider of 3. Note that the

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Figure 14-86. UPM Synchronization Cycle

Table 14-45. UPM Synchronization Cycles

Compensation Cycle

is intended to compensate for the reaction time

Local Bus Controller