MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 786

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 15-28
15.5.3.3.4
The RQUEUE register enables each of the RxBD rings 0–7. By default, RxBD ring 0 is enabled.
Figure 15-25
Table 15-29
15-54
11–15
16–31
Offset eTSEC1:0x2_4314; eTSEC3:0x2_5314
Reset
3–10
\
Bits
Bits
0–7
0
1
2
8
W
R
0
0 0 0 0 0 0 0 0
Name
Name
ICEN
ICCS Interrupt coalescing timer clock source.
ICFT
ICTT
EX0
—
—
—
describes the fields of the RXIC register.
describes the RQUEUE register.
—
describes the definition for the RQUEUE register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Receive Queue Control Register (RQUEUE)
Interrupt coalescing enable
0 Interrupt coalescing is disabled. Interrupts are raised as they are received.
1 Interrupt coalescing is enabled. If the eTSEC receive frame interrupt is enabled (IMASK[RXFEN] is set),
0 The coalescing timer advances count every 64 eTSEC Rx interface clocks (TSECn_GTX_CLK).
1 The coalescing timer advances count every 64 system clocks. This mode is recommended for FIFO
Reserved
Interrupt coalescing frame count threshold. While interrupt coalescing is enabled (RXIC[ICE] is set), this value
determines how many frames are received before raising an interrupt. The eTSEC threshold counter is reset
to ICFT following an interrupt. The value of ICFT must be greater than zero avoid unpredictable behavior.
Reserved
Interrupt coalescing timer threshold. While interrupt coalescing is enabled (RXIC[ICE] is set), this value
determines the maximum amount of time after receiving a frame before raising an interrupt. If frames have
been received but the frame count threshold has not been met, an interrupt is raised when the threshold timer
reaches zero. The threshold timer is reset to the value in this field and begins counting down upon receiving
the first frame having its RxBD[I] bit set. The threshold value is represented in units equal to 64 periods of the
clock specified by RXIC[ICCS]. ICTT must be greater than zero to avoid unpredictable behavior.
Reserved
Receive queue 0 extract enable.
0 Data transferred by DMA to this RxBD ring is not extracted to cache.
1 Data transferred by DMA to this RxBD ring undergoes extraction according to ATTR register.
an interrupt is raised when the threshold number of frames is reached (defined by RXIC[ICFT]) or when
the threshold timer expires (determined by RXIC[ICTT]).
operation.
7
EX0 EX1 EX2 EX3 EX4 EX5 EX6 EX7
8
1
0
9
10
0
Figure 15-25. RQUEUE Register Definition
Table 15-29. RQUEUE Field Descriptions
Table 15-28. RXIC Field Descriptions
11
0
12
0
13
0
14
0
15
0
Description
Description
16
0 0 0 0 0 0 0 0
—
23
EN0 EN1 EN2 EN3 EN4 EN5 EN6 EN7
24
1
25
0
26
0
Freescale Semiconductor
27
0
Access: Read/Write
28
0
29
0
30
0
31
0