MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 179

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.4.3.16
The PCI clock source inputs, shown in
for the PCIinterface. See Section
that the value latched on this signal during POR is accessible through the memory-mapped PORDEVSR
(POR device status register) described in Section 18.4.1.4, “POR Device Status Register (PORDEVSR).”
4.4.3.17
The PCI speed configuration input, shown in
with the PCI clock frequencies in use. The default setting is appropriate for PCI operating above 33 MHz.
For low speed operation (PCI at or below 33 MHZ) this POR configuration input should be low during
HRESET. If this configuration is not set properly, behavior of the PCI interface may be unreliable. Note
that the value latched on this signal during POR is accessible through the memory-mapped PORDEVSR,
described in
4.4.3.18
The PCI I/O impedance configuration inputs, shown in
drivers for the respective interfaces. Note that the values latched on these signals during POR are
accessible through PORIMPSCR, described in
Register (PORIMPSCR).”
Freescale Semiconductor
PCI_GNT[4]
Functional
TSEC3_TXD[3]
Default (1)
Functional
Signal
Default (0)
Signal
Functional Signal Reset Configuration Name
PCI_GNT[3]
Default (1)
Reset Configuration
Section 19.4.1.4, “POR Device Status Register (PORDEVSR).”
PCI Clock Selection
PCI Speed Configuration
PCI I/O Impedance
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reset Configuration
cfg_srds_sgmii_refclk
cfg_pci_clk
Name
Name
Table 4-24. SGMII SerDes Reference Clock Configuration
cfg_pci_speed
(Binary)
Value
Section 4.4.4.1, “System Clock/PCI
0
1
Table 4-26. PCI Speed Configuration
(Binary)
Value
Table 4-25
Table 4-25. PCI Clock Select
0
1
Asynchronous mode. PCI_CLK is used as the clock for the PCI interface
Synchronous mode. SYSCLK is used as the clock for the PCI interface. (default)
SGMII SerDes expects a 100MHz reference clock frequency (default).
SGMII SerDes expects a 125MHz reference clock frequency.
Table
Section 19.4.1.3, “POR I/O Impedance Status and Control
specify the clock mode (synchronous or asynchronous)
(Binary)
Value
4-26, configures internal logic for proper operation
0
1
Table 4-27
PCI frequency at or below 33 MHz
PCI frequency above 33 MHz
(default)
select the impedance of the PCI I/O
Meaning
Clock” for more information. Note
Meaning
Meaning
Reset, Clocking, and Initialization
4-21