MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 990
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MPC8544COMEDEV
Manufacturer Part Number
MPC8544COMEDEV
Description
KIT DEV EXPRESS MPC8544COM
Manufacturer
Freescale Semiconductor
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544COMEDEV
Contents
Board
For Use With/related Products
MPC8544
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PCI Bus Interface
17.2
Figure 17-2
Table 17-2
17-6
PCI_AD[31:0]
Signal
External Signal Descriptions
contains the detailed descriptions of the external PCI interface signals.
shows the external PCI signals.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I/O
I/O PCI address/data bus. The PCI address/data bus consists of signals that are both input and output
O As outputs for the bidirectional PCI address/data bus, these signals operate as described below.
I As inputs for the bidirectional PCI address/data bus, these signals operate as described below.
Table 17-2. PCI Interface Signals—Detailed Signal Descriptions
signals on this PCI controller.
Meaning
Meaning
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Arbitration
Command
Reporting
State
State
and Data
Interface
Address
37 signals
10 signals
6 signals
2 signals
Error
Asserted/Negated—Represents the physical address during the address phase of a PCI
Asserted/Negated—Represents the address to be decoded as a check for device select
Figure 17-2. PCI Interface External Signals
transaction. During the data phase(s) of a PCI transaction, the PCI address/data bus
contain the data being written.
The PCI_AD[7:0] signals define the LSB and PCI_AD[31:24] the MSB.
during the address phase of a PCI transaction or the data being received during the
data phase(s) of a PCI transaction.
The PCI_AD[7:0] signals define the LSB and PCI_AD[31:24] the MSB.
PCI_AD[31:0]
PCI_C/BE[3:0]
PCI_PAR
PCI_FRAME
PCI_TRDY
PCI_IRDY
PCI_STOP
PCI_DEVSEL
PCI_IDSEL
PCI_PERR
PCI_SERR
PCI_REQ[4:0]
PCI_GNT[4:0]
PCI_CLK
Description
32
4
1
1
1
1
1
1
1
1
1
5
5
1
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