MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 40

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
18.3.10.2
18.3.10.3
18.3.10.4
18.3.10.5
18.3.10.6
18.3.10.7
18.3.10.8
18.3.10.9
18.3.10.10
18.3.10.11
18.3.10.12
18.3.10.13
18.3.10.14
18.3.10.15
18.3.10.16
18.3.10.17
18.3.10.18
18.3.10.19
18.3.10.20
18.4
18.4.1
18.4.1.1
18.4.1.2
18.4.1.2.1
18.4.1.3
18.4.1.4
18.4.1.5
18.4.1.6
18.4.1.7
18.4.1.8
18.4.1.8.1
18.4.1.8.2
18.4.2
18.4.2.1
18.4.2.1.1
18.4.2.1.2
18.4.2.1.3
18.4.2.1.4
18.4.2.2
18.4.2.2.1
18.4.2.2.2
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MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Functional Description................................................................................................. 18-97
Architecture ............................................................................................................. 18-98
Interrupts............................................................................................................... 18-106
PCI Express Uncorrectable Error Status Register—0x104 ................................. 18-82
PCI Express Uncorrectable Error Mask Register—0x108 .................................. 18-83
PCI Express Uncorrectable Error Severity Register—0x10C ............................. 18-84
PCI Express Correctable Error Status Register—0x110 ..................................... 18-85
PCI Express Correctable Error Mask Register—0x114 ...................................... 18-85
PCI Express Advanced Error Capabilities and Control Register—0x118 .......... 18-86
PCI Express Header Log Register—0x11C–0x12B ............................................ 18-87
PCI Express Root Error Command Register—0x12C......................................... 18-88
PCI Express Root Error Status Register—0x130 ................................................ 18-88
PCI Express Correctable Error Source ID Register—0x134............................... 18-89
PCI Express Error Source ID Register—0x136 .................................................. 18-89
LTSSM State Status Register—0x404................................................................. 18-90
PCI Express Controller Core Clock Ratio Register—0x440............................... 18-91
PCI Express Power Management Timer Register—0x450 ................................. 18-92
PCI Express PME Time-Out Register (EP-Mode Only)—0x454 ....................... 18-93
PCI Express Subsystem Vendor ID Update Register (EP Mode Only)—0x478. 18-94
Configuration Ready Register—0x4B0............................................................... 18-94
PME_To_Ack Timeout Register (RC-Mode Only)—0x590............................... 18-95
Secondary Status Interrupt Mask Register (RC-Mode Only)—0x5A0 ............... 18-95
PCI Express Transactions .................................................................................... 18-98
Byte Ordering ...................................................................................................... 18-99
Transaction Ordering Rules ............................................................................... 18-101
Memory Space Addressing................................................................................ 18-101
I/O Space Addressing ........................................................................................ 18-101
Configuration Space Addressing ....................................................................... 18-102
Serialization of Configuration and I/O Writes................................................... 18-102
Messages............................................................................................................ 18-102
EP Interrupt Generation ..................................................................................... 18-106
RC Handling of INTx Message and MSI Interrupt ........................................... 18-107
Byte Order for Configuration Transactions ................................................... 18-100
Outbound ATMU Message Generation ......................................................... 18-102
Inbound Messages ......................................................................................... 18-104
Hardware INTx Message Generation ............................................................ 18-106
Hardware MSI Generation............................................................................. 18-106
Software INTx Message Generation ............................................................. 18-106
Software MSI Generation.............................................................................. 18-106
INTx Message Handling................................................................................ 18-107
MSI Handling ................................................................................................ 18-107
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