MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1189

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.4.1.23 Clock Out Control Register (CLKOCR)
Shown in
the clock out (CLK_OUT) signal.
Table 19-26
Freescale Semiconductor
Offset 0xE_0E00
Reset
Bits
30
31
26–31 CLK_SEL Clock out select
1–25
Bits
W
R
0
ENB
0
Figure
describes the bit settings of CLKOCR.
1
Name
ENB
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
MCK4_DIS
MCK5_DIS
19-23, the CLKOCR contains control bits that select the clock sources to be placed on
Name
Clock out enable
0 CLK_OUT signal is three-stated
1 CLK_OUT signal is driven according to CLKOCR[CLK_SEL]
Reserved
000000CCB (platform) clock
000001CCB (platform) clock divided by 2
000010SYSCLK (echoes SYSCLK input)
000011SYSCLK divided by 2 (demonstrates
000100Reserved
000101Reserved
000110Reserved
000111Reserved
001000Reserved
001001Reserved
001010Reserved
001011Reserved
001100Reserved
001101Reserved
001110Reserved
001111Reserved
01xx0xReserved
Table 19-25. DDRCLKDR Field Descriptions (continued)
Figure 19-23. Clock Out Control Register (CLKOCR)
platform PLL lock)
DDR clock 4 disable
0 MCK4 is enabled.
1 MCK4 is disabled.
DDR clock 5 disable
0 MCK5 is enabled.
1 MCK5 is disabled.
Table 19-26. CLKOCR Field Descriptions
—
All zeros
Description
01xx1xReserved
10x000Reserved
10x001Reserved
10x010PCI bus clock
10x011PCI bus clock divided by 2
10x100Reserved
10x101Reserved
10x110Reserved
10x111Logic 0
11x000Reserved
11x001Reserved
11x010Reserved
11x011Reserved
11x100Reserved
11x101Reserved
11x110Reserved
11x111Logic 1
Description
25 26
Access: Read/Write
CLK_SEL
Global Utilities
19-23
31