MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 720

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Local Bus Controller

The connections are specified as follows:

One chip select, LCSn (whatever is available in the system), is used to memory map accesses from

the host local bus to the HDI16 MSC8101 HDI16 peripheral, and is connected to the HDI16 chip

select line (HCS).

This interface uses two separate general-purpose strobe lines (LGPL1 and LGPLy):

— LGPL1 is programmed to generate the HDI16 read/write signal (HRDRW), which is typically

— LGPLy is programmed to generate the HDI16 data strobe (HDS), which must be asserted every

Data lines—The bus data lines (LADn) are directly connected to the HDI16 data lines (HDn).

DMA request/service request signals (HRRQ and HTRQ)—as appropriate in the application

high for a read access and low for write access. In any case, the host port requires a HR/W

signal. This can be generated by using LGPL1, and allows it to adopt the timing virtually

without restrictions. Alternatively the designer can invert LBCTL to generate this signal. It is

the responsibility of the UPM pattern designer to plan for the additional delay of that inverter

in the UPM pattern to satisfy the AC timings at the DSP host port.

16-bit read or write transaction.

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Local Bus Interface

Table 14-44. Local Bus to MSC8101 HDI16 Connections (continued)

or inverted LBCTL

in application

Figure 14-81. Interface to MSC8101 HDI16

Host data strobe signal

Receive host request OP

Transmit host request OP

As required in application

Connect with Local Bus Signal

Freescale Semiconductor