MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 296

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

L2 Look-Aside Cache/SRAM
Stashing is controlled either by an attribute from the initiator of a write or by address range registers in the
L2 cache. New cache lines are allocated for full-cache-line writes (unless the line is already resident in the
cache). Sub-cache-line write data is stashed only if the line is already valid in the cache. For these
sub-cache-line writes, a read-modify-write process is used to merge the write data with the valid data
already in the cache.
For information on how to initiate cache stashing from an I/O master, see the respective chapters for the
I/O masters that support stashing.
For address range based control of stashing, the L2 cache external write address registers 0–3
(L2CEWARn) and the L2 cache external write address registers extended address 0–3 (L2CEWAREAn)
are used with the L2 cache external write control registers 0–3 (L2CEWCRn) to control the cache stashing
functionality. Each register set (for example L2CEWAR0, L2CEWAREA0, and L2CEWCR0) specifies a
programmed memory range that can be allocated and optionally locked with a global write transaction.
The address register must be naturally aligned to the window size in the corresponding control register.
For more information, see
Section 7.3.1.2, “L2 Cache External Write Registers.”
Note that stashing can occur regardless of whether the L1 cache is enabled or whether the cache-inhibited
bit in the MMU is set for the page.
7.4.1
Stash-Only Cache Regions
In order to prevent stashed I/O data from polluting processor data in the L2 cache (and vice versa), it is
possible to create stash-only regions. This is controlled by the L2STASHCTL field of L2CTL. See
Section 7.3.1.1, “L2 Control Register (L2CTL).”
If a stash-only region is created, then that region of the cache will only be used for stashed I/O data, and
stashed I/O data will not cause the eviction of processor data; they are kept in separate ways of each set.
The processor may allocate data into the ways of the cache that are not allocated to SRAM or stash-only
memory. Replacement within the stash-only region and the processor region will be governed by a
pseudo-LRU algorithm modified by masks that allow only applicable ways of a cache set to be considered
for replacement.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
7-26
Freescale Semiconductor