DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 131

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
3.2.3
BCR is an 8-bit readable/writable register that specifies the external memory space access mode,
and the I/O area range when the AS pin is designated for use as the I/O strobe. For details on bits 7
to 2, see section 6.2.1, Bus Control Register (BCR).
BCR is initialized to H'D7 by a reset and in hardware standby mode.
Bits 1 and 0—IOS Select 1 and 0 (IOS1, IOS0): These bits specify the addresses for which the
AS/IOS pin output goes low when IOSE = 1.
Note:
Bit 0
RAME
0
1
Bit 1
IOS1
0
1
Bit
Initial value
Read/Write
* In the H8S/2138 F-ZTAT A-mask version, the address range is from H'(FF)F000 to
Bus Control Register (BCR)
BCR
H'(FF)F7FF.
Description
On-chip RAM is disabled
On-chip RAM is enabled
Bit 0
IOS0
0
1
0
1
ICIS1
R/W
7
1
Description
The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)F03F
The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)F0FF
The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)F3FF
The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)FE4F *
ICIS0
R/W
6
1
BRSTRM
R/W
5
0
BRSTS1
R/W
4
1
BRSTS0
Rev. 4.00 Jun 06, 2006 page 75 of 1004
R/W
3
0
Section 3 MCU Operating Modes
R/W
—
2
1
IOS1
R/W
REJ09B0301-0400
1
1
(Initial value)
(Initial value)
IOS0
R/W
0
1