DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 652

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 21 ROM
Automatic SCI Bit Rate Adjustment
When boot mode is initiated, the H8S/2138 or H8S/2134 Group MCU measures the low period of
the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI
transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The MCU
calculates the bit rate of the transmission from the host from the measured low period, and
transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should
confirm that this adjustment end indication (H'00) has been received normally, and transmit one
H'55 byte to the MCU. If reception cannot be performed normally, initiate boot mode again
(reset), and repeat the above operations. Depending on the host’s transmission bit rate and the
MCU’s system clock frequency, there will be a discrepancy between the bit rates of the host and
the MCU. To ensure correct SCI operation, the host’s transfer bit rate should be set to (2400,
4800, or 9600) bps.
Table 21.7 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the MCU’s bit rate is possible. The boot program should be executed within this
system clock range.
Table 21.7 System Clock Frequencies for which Automatic Adjustment of H8S/2138 or
Host Bit Rate
9600 bps
4800 bps
2400 bps
Rev. 4.00 Jun 06, 2006 page 596 of 1004
REJ09B0301-0400
Figure 21.9 RxD1 Input Signal When Using Automatic SCI Bit Rate Adjustment
H8S/2134 Group Bit Rate Is Possible
(Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT)
Start
bit
D0
System Clock Frequency for which Automatic Adjustment
of H8S/2138 or H8S/2134 Group Bit Rate Is Possible
8 MHz to 20 MHz
4 MHz to 20 MHz
2 MHz to 18 MHz
Low period (9 bits) measured (H'00 data)
D1
D2
D3
D4
D5
D6
D7
(1 or more bits)
High period
Stop
bit