DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 459

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in
asynchronous mode, causing abnormal termination.
Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is
Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity
addition in asynchronous mode, causing abnormal termination.
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is
Bit 4
FER
0
1
Bit 3
PER
0
1
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit
2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not
cleared to 0.
is not checked. If a framing error occurs, the receive data is transferred to RDR but the
RDRF flag is not set. Also, subsequent serial reception cannot be continued while the
FER flag is set to 1. In synchronous mode, serial transmission cannot be continued,
either.
cleared to 0.
set. Also, subsequent serial reception cannot be continued while the PER flag is set to
1. In synchronous mode, serial transmission cannot be continued, either.
Description
[Clearing condition]
When 0 is written in FER after reading FER = 1
[Setting condition]
When the SCI checks the stop bit at the end of the receive data when reception ends,
and the stop bit is 0 *
Description
[Clearing condition]
When 0 is written in PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit does not
match the parity setting (even or odd) specified by the O/E bit in SMR *
2
Section 15 Serial Communication Interface (SCI, IrDA)
Rev. 4.00 Jun 06, 2006 page 403 of 1004
REJ09B0301-0400
2
(Initial value) *
(Initial value) *
1
1