DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 29

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.2 Register Descriptions ........................................................................................................ 460
16.3 Operation .......................................................................................................................... 485
16.4 Usage Notes ...................................................................................................................... 506
Section 17 Host Interface [H8S/2138 Group]
17.1 Overview........................................................................................................................... 523
17.2 Register Descriptions ........................................................................................................ 527
16.1.3 Input/Output Pins ................................................................................................. 458
16.1.4 Register Configuration......................................................................................... 459
16.2.1 I
16.2.2 Slave Address Register (SAR) ............................................................................. 463
16.2.3 Second Slave Address Register (SARX) ............................................................. 464
16.2.4 I
16.2.5 I
16.2.6 I
16.2.7 Serial Timer Control Register (STCR) ................................................................ 480
16.2.8 DDC Switch Register (DDCSWR) ...................................................................... 481
16.2.9 Module Stop Control Register (MSTPCR) .......................................................... 484
16.3.1 I
16.3.2 Master Transmit Operation .................................................................................. 487
16.3.3 Master Receive Operation.................................................................................... 489
16.3.4 Slave Receive Operation...................................................................................... 492
16.3.5 Slave Transmit Operation .................................................................................... 495
16.3.6 IRIC Setting Timing and SCL Control ................................................................ 496
16.3.7 Automatic Switching from Formatless Mode to I
16.3.8 Operation Using the DTC .................................................................................... 499
16.3.9 Noise Canceler ..................................................................................................... 500
16.3.10 Sample Flowcharts............................................................................................... 500
16.3.11 Initialization of Internal State .............................................................................. 505
17.1.1 Features................................................................................................................ 523
17.1.2 Block Diagram ..................................................................................................... 524
17.1.3 Input and Output Pins .......................................................................................... 525
17.1.4 Register Configuration......................................................................................... 526
17.2.1 System Control Register (SYSCR) ...................................................................... 527
17.2.2 System Control Register 2 (SYSCR2) ................................................................. 528
17.2.3 Host Interface Control Register (HICR) .............................................................. 529
17.2.4 Input Data Register 1 (IDR1)............................................................................... 530
17.2.5 Output Data Register 1 (ODR1)........................................................................... 530
17.2.6 Status Register 1 (STR1) ..................................................................................... 531
17.2.7 Input Data Register 2 (IDR2)............................................................................... 532
17.2.8 Output Data Register 2 (ODR2)........................................................................... 533
2
2
2
2
2
C Bus Data Register (ICDR) ............................................................................. 460
C Bus Mode Register (ICMR) ........................................................................... 465
C Bus Control Register (ICCR) ......................................................................... 468
C Bus Status Register (ICSR)............................................................................ 475
C Bus Data Format ............................................................................................ 485
............................................................. 523
Rev. 4.00 Jun 06, 2006 page xxvii of liv
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C Bus Format ........................ 498