DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 755

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

24.8
24.8.1
If a SLEEP instruction is executed in high-speed mode or subactive mode when the SSBY in
SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1)
is set to 1, the CPU makes a transition to watch mode.
In this mode, the CPU and all on-chip supporting modules except WDT1 stop. As long as the
prescribed voltage is supplied, the contents of some of the CPU’s internal registers and on-chip
RAM are retained, and I/O ports retain their states prior to the transition.
24.8.2
Watch mode is cleared by an interrupt (WOVI1 interrupt, NMI pin, or pin IRQ0, IRQ1, IRQ2,
IRQ6, or IRQ7), or by means of the RES pin or STBY pin.
Clearing with an Interrupt: When an interrupt request signal is input, watch mode is cleared and
a transition is made to high-speed mode or medium-speed mode if the LSON bit in LPWRCR is
cleared to 0, or to subactive mode if the LSON bit is set to 1. When making a transition to high-
speed mode, after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are
supplied to the entire chip, and interrupt exception handling is started.
Watch mode cannot be cleared with an IRQ0, IRQ1, IRQ2, IRQ6, or IRQ7 interrupt if the
corresponding enable bit has been cleared to 0, or with an on-chip supporting module interrupt if
acceptance of the relevant interrupt has been disabled by the interrupt enable register or masked by
the CPU.
See section 24.6.3, Setting Oscillation Settling Time after Clearing Software Standby Mode, for
the oscillation settling time setting when making a transition from watch mode to high-speed
mode.
Clearing with the RES
Software Standby Mode.
Clearing with the STBY
standby mode.
Watch Mode
Clearing Watch Mode
Watch Mode
RES
RES
RES Pin: See “Clearing with the RES Pin” in section 24.6.2, Clearing
STBY
STBY
STBY Pin: When the STBY pin is driven low, a transition is made to hardware
Rev. 4.00 Jun 06, 2006 page 699 of 1004
Section 24 Power-Down State
REJ09B0301-0400