DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 22

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.2
6.3
6.4
6.5
6.6
6.7
Section 7 Data Transfer Controller [H8S/2138 Group]
7.1
7.2
Rev. 4.00 Jun 06, 2006 page xx of liv
6.1.1
6.1.2
6.1.3
6.1.4
Register Descriptions ........................................................................................................ 140
6.2.1
6.2.2
Overview of Bus Control .................................................................................................. 143
6.3.1
6.3.2
6.3.3
6.3.4
Basic Bus Interface ........................................................................................................... 146
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
Burst ROM Interface......................................................................................................... 153
6.5.1
6.5.2
6.5.3
Idle Cycle .......................................................................................................................... 155
6.6.1
6.6.2
Bus Arbitration.................................................................................................................. 157
6.7.1
6.7.2
6.7.3
Overview........................................................................................................................... 159
7.1.1
7.1.2
7.1.3
Register Descriptions ........................................................................................................ 162
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
Features................................................................................................................ 137
Block Diagram ..................................................................................................... 138
Pin Configuration................................................................................................. 139
Register Configuration......................................................................................... 139
Bus Control Register (BCR) ................................................................................ 140
Wait State Control Register (WSCR) .................................................................. 141
Bus Specifications................................................................................................ 143
Advanced Mode................................................................................................... 144
Normal Mode....................................................................................................... 144
I/O Select Signal .................................................................................................. 145
Overview.............................................................................................................. 146
Data Size and Data Alignment............................................................................. 146
Valid Strobes........................................................................................................ 147
Basic Timing........................................................................................................ 148
Wait Control ........................................................................................................ 151
Overview.............................................................................................................. 153
Basic Timing........................................................................................................ 153
Wait Control ........................................................................................................ 155
Operation ............................................................................................................. 155
Pin States in Idle Cycle ........................................................................................ 156
Overview.............................................................................................................. 157
Operation ............................................................................................................. 157
Bus Transfer Timing ............................................................................................ 158
Features................................................................................................................ 159
Block Diagram ..................................................................................................... 160
Register Configuration......................................................................................... 161
DTC Mode Register A (MRA) ............................................................................ 162
DTC Mode Register B (MRB)............................................................................. 164
DTC Source Address Register (SAR).................................................................. 165
DTC Destination Address Register (DAR).......................................................... 165
DTC Transfer Count Register A (CRA) .............................................................. 165
............................................ 159