DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 704

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 22 ROM
Rev. 4.00 Jun 06, 2006 page 648 of 1004
REJ09B0301-0400
Note: Use a (z3) s write pulse for additional
Notes: 1. Data transfer is performed by byte transfer.
Note 7: Write Pulse Width
Number of Writes n
Write pulse application subroutine
Wait (z1) s, (z2) s or (z3) s
programming.
Program Data Computation Chart
1000
2. Verify data is read in 16-bit (word) units.
3. Even bits for which programming has been completed
4. A 128-byte area for storing program data, a 128-byte area
5. The write pulse of (z1) s or (z2) s is applied according to the progress of the programming operation. See Note 7 for the pulse widths. When writing of additional
6. See section 25, Electrical Characteristics, Flash Memory Characteristics, for the values of x, y, z1, z2, z3, , , , , , , and N.
Clear PSU bit in FLMCR2
Original Data
998
999
Set PSU bit in FLMCR2
10
11
12
13
Sub-routine write pulse
storage area (128 kbytes)
Clear P bit in FLMCR1
1
2
3
4
5
6
7
8
9
. .
.
Additional program data
Reprogram data storage
Set P bit in FLMCR1
The lower 8 bits of the first address written to must be
H'00 or H'80. A 128-byte data transfer must be
performed even if writing fewer than 128 bytes; in this
case, H'FF data must be written to the extra addresses.
in the 128-byte programming loop will be subjected to
additional programming if they fail the subsequent
verify operation.
for storing reprogram data, and a 128-byte area for storing
additional program data must be provided in RAM. The reprogram and additional program data contents are modified as programming proceeds.
program data is executed, a (z3) µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
Program data storage
(D)
Disable WDT
area (128 bytes)
0
1
Enable WDT
area (128 bytes)
Wait ( ) s
Wait ( ) s
Wait (y) s
End sub
RAM
Verify Data
Write Time (z) s
(V)
0
1
0
1
(H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version)
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
. .
.
Reprogram
Figure 22.12 Program/Program-Verify Flowchart
Data (X)
1
0
1
1
*5
Increment address
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Comments
Transfer reprogram data to reprogram data area *4
Write 128-byte data in additional program data
Store 128-byte program data in program
area in RAM consecutively to flash memory
NG
Write 128-byte data in RAM reprogram data
data area and reprogram data area
Additional program data computation
H'FF dummy write to verify address
Transfer additional program data
area consecutively to flash memory
to additional program data area
Reprogram data computation
Additional write pulse (z3) s
Clear SWE bit in FLMCR1
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set PV bit in FLMCR1
Start of programming
End of programming
(z1) s or (z2) s
Read verify data
data verification?
End of 128-byte
Program data =
Wait ( ) s
Wait (x) s
Wait ( ) s
Wait ( ) s
Write pulse
Wait ( ) s
verify data?
OK
OK
OK
m = 0?
m = 0
6
n = 1
6
Start
Additional Program Data Computation Chart
n?
Reprogram
OK
n?
OK
Data (X')
0
1
Sub-routine-call
Verify Data
(V)
0
1
0
1
NG
NG
NG
NG
*4
*1
See Note 7 for pulse width
*2
*4
*3
*1
Additional Program
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
m = 1
Data (Y)
0
1
1
1
Clear SWE bit in FLMCR1
Programming failure
Additional programming executed
Additional programming not executed
Additional programming not executed
Wait ( ) s
n
1000?
OK
Comments
NG
n
n + 1