DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 807

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 25.22 Timing of On-Chip Supporting Modules (2)
Condition A: V
Condition B: V
Condition C: V
Item
HIF read
cycle
HIF write
cycle
CS/HA0 setup item
CS/HA0 hold time
IOR pulse width
HDB delay time
HDB hold time
HIRQ delay time
CS/HA0 setup item
CS/HA0 hold time
IOW pulse width
HDB
setup
time
HDB hold time
GA20 delay time
T
T
T
T
T
a
a
a
a
a
CC
CC
CC
= –20 to +75°C (regular specifications),
= –40 to +85°C (wide-range specifications)
= –20 to +75°C (regular specifications),
= –40 to +85°C (wide-range specifications)
= –20 to +75°C
= 5.0 V ±10%, V
= 4.0 V to 5.5 V, V
= 2.7 V to 3.6 V, V
Fast A20
gate not
used
Fast A20
gate used
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
HAR
HRA
HRPW
HRD
HRF
HIRQ
HAW
HWA
HWPW
HDW
HWD
HGA
SS
= 0 V, = 2 MHz to maximum operating frequency,
SS
SS
= 0 V, = 2 MHz to maximum operating frequency,
= 0 V, = 2 MHz to maximum operating frequency,
Min
10
10
120
—
0
—
10
10
60
30
45
15
—
Condition A
20 MHz
Max
—
—
—
100
25
120
—
—
—
—
—
—
90
Min
Condition B
10
10
120
—
0
—
10
10
60
30
55
15
—
Rev. 4.00 Jun 06, 2006 page 751 of 1004
16 MHz
Max
—
—
—
100
25
120
—
—
—
—
—
—
90
Section 25 Electrical Characteristics
Condition C
Min
10
10
220
—
0
—
10
10
100
50
85
25
—
10 MHz
Max
—
—
—
200
40
200
—
—
—
—
—
—
180
REJ09B0301-0400
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test
Conditions
Figure 25.25