DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 26

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.4 Interrupts ........................................................................................................................... 296
11.5 Sample Application........................................................................................................... 297
11.6 Usage Notes ...................................................................................................................... 298
Section 12 8-Bit Timers
12.1 Overview........................................................................................................................... 305
12.2 Register Descriptions ........................................................................................................ 309
12.3 Operation .......................................................................................................................... 325
12.4 Interrupt Sources............................................................................................................... 333
12.5 8-Bit Timer Application Example..................................................................................... 334
12.6 Usage Notes ...................................................................................................................... 335
Rev. 4.00 Jun 06, 2006 page xxiv of liv
11.3.7 Setting of FRC Overflow Flag (OVF) ................................................................. 294
11.3.8 Automatic Addition of OCRA and OCRAR/OCRAF ......................................... 294
11.3.9 ICRD and OCRDM Mask Signal Generation ...................................................... 295
12.1.1 Features................................................................................................................ 305
12.1.2 Block Diagram ..................................................................................................... 306
12.1.3 Pin Configuration................................................................................................. 307
12.1.4 Register Configuration......................................................................................... 308
12.2.1 Timer Counter (TCNT)........................................................................................ 309
12.2.2 Time Constant Register A (TCORA)................................................................... 310
12.2.3 Time Constant Register B (TCORB) ................................................................... 311
12.2.4 Timer Control Register (TCR) ............................................................................. 312
12.2.5 Timer Control/Status Register (TCSR) ................................................................ 315
12.2.6 Serial Timer Control Register (STCR) ................................................................ 319
12.2.7 System Control Register (SYSCR) ...................................................................... 320
12.2.8 Timer Connection Register S (TCONRS)............................................................ 320
12.2.9 Input Capture Register (TICR) [TMRX Additional Function] ............................ 321
12.2.10 Time Constant Register C (TCORC) [TMRX Additional Function]................... 322
12.2.11 Input Capture Registers R and F (TICRR, TICRF)
12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function]..................... 323
12.2.13 Module Stop Control Register (MSTPCR) .......................................................... 324
12.3.1 TCNT Incrementation Timing ............................................................................. 325
12.3.2 Compare-Match Timing....................................................................................... 326
12.3.3 TCNT External Reset Timing .............................................................................. 328
12.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 328
12.3.5 Operation with Cascaded Connection.................................................................. 329
12.3.6 Input Capture Operation ...................................................................................... 330
12.6.1 Contention between TCNT Write and Clear........................................................ 335
12.6.2 Contention between TCNT Write and Increment ................................................ 336
12.6.3 Contention between TCOR Write and Compare-Match ...................................... 337
[TMRX Additional Functions]............................................................................. 322
..................................................................................................... 305