DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 544

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 I
[7] When one frame of data has been transimitted, the IRIC flag is set to 1 at the rise of the 9th
[8] Read the ACKB bit to confirm that ACKB is 0. When the slave device has not returned an
[9] Write the next data to be transmitted in ICDR. To indicate the end of data transfer, clear the
[10] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
[11] Read the ACKB bit of ICSR. Confirm that the slave device has returned an acknowledge
[12] Clear the IRIC flag to 0. Write BBSY and SCP of ICCR to 0. By doing so, SDA is changed
Rev. 4.00 Jun 06, 2006 page 488 of 1004
REJ09B0301-0400
Writing to ICDR and clearing of the IRIC flag must be executed continuously, so that no
interrupt is inserted.
If a period of time that is equal to transfer one byte has elapsed by the time the IRlC flag is
cleared, the end of transfer cannot be identified.
The master device sequentially sends the transmit clock and the data written to ICDR with the
timing shown in figure 16.7. The selected slave device (i.e. , the slave device with the
matching slave address) drives SDA low at the 9th transmit clock pulse and returns an
acknowledge signal.
transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
acknowledge signal and ACKB remains 1, execute the transmit end processing described in
step [12] and perfrom transmit operation again.
IRIC flag to 0.
As described in step [6] above, writing to ICDR and clearing of the IRIC flag must be
executed continuously so that no interrupt is inserted.
The next frame is transmitted in synchronization with the internal clock.
transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
signal and ACKB is 0. When more data is to be transmitted, return to step [9] to execute next
transmit operation. If the slave device has not returned an acknowledge signal and ACKB is 1,
execute the transmit end processing described in step [12].
from low to high while SCL is high and the transmit stop condition is generated.
2
C Bus Interface [H8S/2138 Group Option]