DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 545

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.3.3
In master receive mode, the master device outputs the receive clock, receives data, and returns an
acknowledge signal. The slave device transrnits data.
The receive procedure and operations by which data is sequentially received in synchronization
with ICDR read operations, are described below.
[1] Clear the TRS bit of ICCR to 0 and switch from transmit mode to receive mode. Set the
[2] When ICDR is read (dummy data read), reception is started and the receive clock is output,
Note: Data write
User processing
timing in ICDR
(slave output)
(master output)
(master output)
WAIT bit to 1 and clear the ACKB bit of ICSR to 0 (acknowledge data setting).
and data is received, in synchronization with the internal clock. To indicate the wait, clear the
IRIC flag to 0.
Reading from ICDR and clearing of the IRIC f1ag must be executed continuously so that no
interrupt is inserted.
If a period of time that is equal to transfer one byte has elapsed by the time the IRIC flag is
cleared, the end of transfer cannot be identified.
SDA
IRTR
ICDR
IRIC
SDA
SCL
ICDR Writing
prohibited
Master Receive Operation
Figure 16.7 Example of Master Transmit Mode Operation Timing
[4] Write BBSY = 1
Start condition
generation
and SCP = 0
(start condition
issuance)
[5]
ICDR Writing
enable
[6] ICDR write
address + R/W
bit 7
1
bit 6
(MLS = WAIT = 0)
2
bit 5
Section 16 I
3
Slave address
bit 4
4
[6] IRIC clear
bit 3
5
Rev. 4.00 Jun 06, 2006 page 489 of 1004
2
C Bus Interface [H8S/2138 Group Option]
bit 2
6
bit 1
7
R/W
bit 0
8
[7]
A
9
[9] ICDR write
REJ09B0301-0400
Data 1
bit 7
1
Data 1
[9] IRIC clear
bit 6
2