DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 38

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 4.2
Figure 4.3
Figure 4.4
Figure 4.5 (1)
Figure 4.5 (2)
Figure 4.6
Section 5 Interrupt Controller
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Figure 5.5
Figure 5.6
Figure 5.7
Figure 5.8
Figure 5.9
Figure 5.10
Figure 5.11
Figure 5.12
Figure 5.13
Section 6 Bus Controller
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
Figure 6.6
Figure 6.7
Figure 6.8 (a)
Figure 6.8 (b)
Figure 6.9
Section 7 Data Transfer Controller [H8S/2138 Group]
Figure 7.1
Figure 7.2
Figure 7.3
Rev. 4.00 Jun 06, 2006 page xxxvi of liv
Reset Sequence (Mode 3) .................................................................................. 95
Reset Sequence (Mode 1) .................................................................................. 96
Interrupt Sources and Number of Interrupts ...................................................... 97
Stack Status after Exception Handling (Normal Mode) .................................... 99
Stack Status after Exception Handling (Advanced Mode) ................................ 99
Operation When SP Value Is Odd ..................................................................... 100
Block Diagram of Interrupt Controller .............................................................. 102
Relationship between Interrupts IRQ6, Interrupts KIN7 to KIN0,
and Registers KMIMR ...................................................................................... 110
Block Diagram of Interrupts IRQ7 to IRQ0 ...................................................... 114
Timing of IRQnF Setting................................................................................... 114
Block Diagram of Address Break Function....................................................... 118
Examples of Address Break Timing.................................................................. 120
Block Diagram of Interrupt Control Operation ................................................. 122
Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control
Mode 0............................................................................................................... 125
Example of State Transitions in Interrupt Control Mode 1 ............................... 126
Flowchart of Procedure Up to Interrupt Acceptance in Interrupt
Control Mode 1 ................................................................................................. 128
Interrupt Exception Handling ............................................................................ 130
Contention between Interrupt Generation and Disabling .................................. 132
Interrupt Control for DTC ................................................................................. 134
Block Diagram of Bus Controller...................................................................... 138
IOS Signal Output Timing................................................................................. 145
Access Sizes and Data Alignment Control (8-Bit Access Space)...................... 146
Access Sizes and Data Alignment Control (16-Bit Access Space).................... 147
Bus Timing for 8-Bit 2-State Access Space ...................................................... 149
Bus Timing for 8-Bit 3-State Access Space ...................................................... 150
Example of Wait State Insertion Timing ........................................................... 152
Example of Burst ROM Access Timing (When AST = BRSTS1 = 1).............. 154
Example of Burst ROM Access Timing (When AST = BRSTS1 = 0).............. 154
Example of Idle Cycle Operation ...................................................................... 156
Block Diagram of DTC ..................................................................................... 160
Flowchart of DTC Operation............................................................................. 169
Block Diagram of DTC Activation Source Control .......................................... 172