DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 757

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

24.10
24.10.1 Subactive Mode
If a SLEEP instruction is executed in high-speed mode when the SSBY bit in SBYCR, the DTON
bit in LPWRCR, and the PSS bit in TCSR (WDT1) are all set to 1, the CPU makes a transition to
subactive mode. When an interrupt is generated in watch mode, if the LSON bit in LPWRCR is
set to 1, a transition is made to subactive mode directly. When an interrupt is generated in subsleep
mode, a transition is made to subactive mode.
In subactive mode, the CPU performs sequential program execution at low speed on the subclock.
In this mode, all on-chip supporting modules except TMR0, TMR1, WDT0, and WDT1 stop.
When operating the device in subactive mode, bits SCK2 to SCK0 in SBYCR must all be cleared
to 0.
24.10.2 Clearing Subactive Mode
Subsleep mode is cleared by a SLEEP instruction, or by means of the RES pin or STBY pin.
Clearing with a SLEEP Instruction: When a SLEEP instruction is executed while the SSBY bit
in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR
(WDT1) is set to 1, subactive mode is cleared and a transition is made to watch mode. When a
SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the LSON bit in
LPWRCR is set to 1, and the PSS bit in TCSR (WDT1) is set to 1, a transition is made to subsleep
mode. When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the
DTON bit is set to 1 and the LSON bit is cleared to 0 in LPWRCR, and the PSS bit in TCSR
(WDT1) is set to 1, a transition is made directly to high-speed mode.
Fort details of direct transition, see section 24.11, Direct Transition.
Clearing with the RES
Software Standby Mode.
Clearing with the STBY
standby mode
Subactive Mode
RES Pin: See “Clearing with the RES Pin” in section 24.6.2, Clearing
RES
RES
STBY
STBY
STBY Pin: When the STBY pin is driven low, a transition is made to hardware
Rev. 4.00 Jun 06, 2006 page 701 of 1004
Section 24 Power-Down State
REJ09B0301-0400