DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 581

IC H8S/2100 MCU FLASH 80QFP

DF2134AFA20V

Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2134AFA20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
17.1.3
Table 17.1 lists the input and output pins of the host interface module.
Table 17.1
Note:
Name
I/O read
I/O write
Chip select 1
Chip select 2 *
Command/data
Data bus
Host interrupt 1
Host interrupt 11
Host interrupt 12
Gate A20
HIF shutdown
* Selection of CS2 or ECS2 is by means of the CS2E bit in SYSCR and the FGA20E bit
Input and Output Pins
in HICR. Host interface channel 2 and the CS2 pin can be used when CS2E = 1. When
CS2E = 1, CS2 is used when FGA20E =0, and ECS2 is used when FGA20E = 1. In this
manual, both are referred to as CS2.
Host Interface Input/Output Pins
Abbreviation
IOR
IOW
CS1
CS2
ECS2
HA0
HDB7 to
HDB0
HIRQ1
HIRQ11
HIRQ12
GA20
HIFSD
Port
P93
P94
P95
P81
P90
P80
P37 to
P30
P44
P43
P45
P81
P82
I/O
Input
Input
Input
Input
Input
I/O
Output
Output
Output
Output
Input
Section 17 Host Interface [H8S/2138 Group]
Function
Host interface read signal
Host interface write signal
Host interface chip select signal for IDR1,
ODR1, STR1
Host interface chip select signal for IDR2,
ODR2, STR2
Host interface address select signal.
In host read access, this signal selects the
status registers (STR1, STR2) or data
registers (ODR1, ODR2). In host write
access to the data registers (IDR1, IDR2),
this signal indicates whether the host is
writing a command or data.
Host interface data bus
Interrupt output 1 to host
Interrupt output 11 to host
Interrupt output 12 to host
A20 gate control signal output
Host interface shutdown control signal
Rev. 4.00 Jun 06, 2006 page 525 of 1004
REJ09B0301-0400

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