DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 330

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 16-Bit Free-Running Timer
11.2.3
There are four input capture registers, A to D, each of which is a 16-bit read-only register.
When the rising or falling edge of the signal at an input capture input pin (FTIA to FTID) is
detected, the current FRC value is copied to the corresponding input capture register (ICRA to
ICRD). At the same time, the corresponding input capture flag (ICFA to ICFD) in TCSR is set to
1. The input capture edge is selected by the input edge select bits (IEDGA to IEDGD) in TCR.
ICRC and ICRD can be used as ICRA and ICRB buffer registers, respectively, and made to
perform buffer operations, by means of buffer enable bits A and B (BUFEA, BUFEB) in TCR.
Figure 11.2 shows the connections when ICRC is specified as the ICRA buffer register (BUFEA =
1). When ICRC is used as the ICRA buffer, both rising and falling edges can be specified as
transitions of the external input signal by setting IEDGA
either the rising or falling edge is designated. See table 11.3.
Note: The FRC contents are transferred to the input capture register regardless of the value of
Rev. 4.00 Jun 06, 2006 page 274 of 1004
REJ09B0301-0400
Read/
Bit
Initial
value
Write
the input capture flag (ICF).
Input Capture Registers A to D (ICRA to ICRD)
FTIA
15
R
0
14
R
0
IEDGA
Figure 11.2 Input Capture Buffering (Example)
13
R
0
generating circuit
Edge detect and
capture signal
12
R
0
BUFEA
11
R
0
ICRC
10
R
0
IEDGC
R
9
0
R
8
0
R
7
0
ICRA
IEDGC. When IEDGA = IEDGC,
R
6
0
R
5
0
R
4
0
R
3
0
FRC
R
2
0
R
1
0
R
0
0