DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 582

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 Host Interface [H8S/2138 Group]
17.1.4
Table 17.2 lists the host interface registers. Host interface registers HICR, IDR1, IDR2, ODR1,
ODR2, STR1, and STR2 can only be accessed when the HIE bit is set to 1 in SYSCR.
Table 17.2 Host Interface Registers
Notes: 1. Bits 5 and 3 are read-only bits.
Rev. 4.00 Jun 06, 2006 page 526 of 1004
REJ09B0301-0400
Name
System control
register
System control
register 2
Host interface
control register
Input data
register 1
Output data
register 1
Status register 1
Input data
register 2
Output data
register 2
Status register 2
Module stop
control register
2. The user-defined bits (bits 7 to 4 and 2) are read/write accessible from the slave
3. Address when accessed from the slave processor. The lower 16 bits of the address are
4. Pin inputs used in access from the host processor.
5. The HA0 input discriminates between writing of commands and data.
Register Configuration
processor.
shown.
Abbreviation
SYSCR
SYSCR2
HICR
IDR1
ODR1
STR1
IDR2
ODR2
STR2
MSTPCRH
MSTPCRL
Slave
R/W *
R/W
R/W
R
R/W
R/(W) *
R
R/W
R/(W) *
R/W
R/W
1
2
2
R/W
Host
—
—
—
W
R
R
W
R
R
—
—
Initial
Value
H'09
H'00
H'F8
—
—
H'00
—
—
H'00
H'3F
H'FF
Slave
Address *
H'FFC4
H'FF83
H'FFF0
H'FFF4
H'FFF5
H'FFF6
H'FFFC
H'FFFD
H'FFFE
H'FF86
H'FF87
3
0
1
CS1
CS1
CS1
CS1
—
—
—
0
0
1
1
—
—
Master Address *
CS2
CS2
CS2
CS2
—
—
—
1
1
1
0
0
0
—
—
HA0
—
—
—
0/1 *
0
1
0/1 *
0
1
—
—
4
5
5