DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 534

IC H8S/2100 MCU FLASH 80QFP

DF2134AFA20V

Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2134AFA20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 16 I
Bit 4
AASX
0
1
Bit 3—Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode. The
I
nearly the same time, if the I
to 1 to indicate that the bus has been taken by another master.
AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is
reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 3
AL
0
1
Bit 2—Slave Address Recognition Flag (AAS): In I
set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the
general call address (H'00) is detected.
Rev. 4.00 Jun 06, 2006 page 478 of 1004
REJ09B0301-0400
2
C bus interface monitors the bus. When two or more master devices attempt to seize the bus at
Description
Second slave address not recognized
[Clearing conditions]
1. When 0 is written in AASX after reading AASX = 1
2. When a start condition is detected
3. In master mode
Second slave address recognized
[Setting condition]
When the second slave address is detected in slave receive mode while FSX = 0
Description
Bus arbitration won
[Clearing conditions]
1. When ICDR data is written (transmit mode) or read (receive mode)
2. When 0 is written in AL after reading AL = 1
Arbitration lost
[Setting conditions]
1. If the internal SDA and SDA pin disagree at the rise of SCL in master transmit
2. If the internal SCL line is high at the fall of SCL in master transmit mode
2
C Bus Interface [H8S/2138 Group Option]
mode
2
C bus interface detects data differing from the data it sent, it sets AL
2
C bus format slave receive mode, this flag is
(Initial value)
(Initial value)

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