hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 123

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

15. IRIG-106 BUS MONITOR (IMT) CONFIGURATION AND OPERATION
The HI-613x is initialized for IRIG-106 Chapter 10 operation (IMT) by resetting bit 0 in the Bus Monitor Configuration
Register 0x0029 to logic 0. The MIL-STD-1553 bus monitors that comply with IRIG-106 produce “data packets” in a
format defined by the IRIG-106 standard. Figure 8 shows the overall data packet structure, comprised of three parts:
a Packet Header, a Packet Body (containing the monitored MIL-STD-1553 message information) and a Packet Trailer.
The HI-613x IMT may be configured to generate complete data IRIG-106 packets, including Packet Header and
Packet Trailer, or may be configured to generate only the Packet Body, without header or trailer. A range of options is
offered for configuring the Packet Header and Packet Trailer.
15.1. Generating complete IRIG-106 Data Packets
IMTHTD bit 3 in the MT Configuration Register 0x0029 is logic 0
The IMT generates the Packet Header and Packet Trailer after the first MIL-STD-1553 message is recorded when
starting a new packet. When each new message data packet is added to the Packet Body, the device updates the
Packet Header and generates a new Packet Trailer. Refer to Figure 8. When one data packet is finalized and the next
data packet begins, the device adjusts the Address List pointers so the new Packet Header starts at the last unwritten
Stack address.
15.2. Generating only IRIG-106 Packet Body (no header or trailer)
IMTHTD bit 3 in the MT Configuration Register 0x0029 is logic 1
The IMT devotes the entire RAM stack for message data packets. For each monitored message, only the Intra-Packet
Timestamp, Intra-Packet Data Header, and Message Data Block are stored, per Figure 10 and the note in Figure 8.
When operated in this mode, the RAM stack is fully utilized for message data; the first Intra-Packet Timestamp occurs
at the stack Start Address initialized in the IMT Address List. The host assumes responsibility for generating the IRIG-
106 Packet Header, Channel Specific Data and Packet Trailer. Otherwise, there may be situations when IMT packet
body structure is simply preferred over SMT storage format, in a non-IRIG application that does not need the header
or trailer overhead.
When operating in IMT mode, MIL-STD-1553 message data is added to the unfinished data packet until the packet
is “finalized.” The host can initiate packet finalization by setting the PKTSTOP bit in the MT Configuration Register.
Criteria for automatic packet finalization can be specified using customized limits. These host-initialized limits for
packet completion are optional, enabled or disabled by configuring limit registers 0x002A through 0x002D. When the
applicable limit register contains zero, that criteria for packet finalization is disabled. The practical maximum value for
each of these limits is actually much smaller than limits shown below, as explained in the descriptions for registers
0x002A through 0x002D.
The data packet ends and packet generation encapsulates the recorded data when the first of the set data packet
limits is reached.
An open IRIG-106 data packet is also finalized when written packet data first crosses within 64 words of overrunning
buffer space. This criteria, imminent buffer overrun, is mandatory and cannot be disabled. The current data packet is
terminated when written packet length is within 64 words of overwriting the Current Packet Start Address (maintained
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host-specified maximum MIL-STD-1553 message count (1 to 65,535) in register 0x002A
host-specified maximum word count (1 to 65,535 words) in register 0x002B
host-specified maximum recording time (655.35 ms max, 10 µs resolution) in register 0x002C
host-specified maximum intermessage gap (655.35 ms max, 10 µs resolution) in register 0x002D
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
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