hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 199

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

20.5. Circular Buffer Mode 1
The device offers two circular data buffer modes as alter-
natives to ping-pong and indexed buffering. These circu-
lar buffer options only apply for subaddress commands,
not mode code commands. Circular buffering simplifies
software servicing of the remote terminal when imple-
menting bulk data transfers. A circular buffer mode can
be selected for any subaddress by properly initializing
its descriptor Control Word. Circular Buffer Mode 1 is
selected when descriptor Control Word PPEN and CI-
R2EN bits are both 0, and the CIR1EN bit is logic 1.
When a subaddress uses circular buffer mode 1, its four
word block in the Descriptor Table is defined as follows:
If Descriptor Word 1 is stored at memory address N, De-
scriptor Word 2 is stored at address N+1, and the other
two words are stored at addresses N+2 and N+3.
Figure 22 provides a generalized illustration of Circular
Buffer Mode 1, while Figure 23 shows a specific exam-
ple. Circular Buffer Mode 1 uses a single user-defined
buffer that merges all transmit or receive data, along
with message information. Two words (Message Infor-
mation and Time-Tag) are stored at the beginning of the
block for each message, followed by the message data
word(s). The Mode 1 buffer pointers roll over (are reset
to their base addresses) when the allocated data buffer
memory is full.
For each valid receive message, the device enters a
Message Information word, Time-Tag word and data
word(s) into the circular receive buffer. For each valid
transmit message, the device enters a Message Infor-
mation word and a Time-Tag word into reserved memory
locations within the circular transmit buffer. The device
automatically controls the wrap around of circular buf-
fers.
Two pointers define circular buffer length: start of buffer
(lowest address) and end of buffer (highest address).
User specifies the start of buffer (SA) by writing the low-
est address value into the second word of a unique sub-
address descriptor block. The user defines the bottom
of the buffer (EA) by writing the highest address value to
the fourth word of that unique descriptor block. Both SA
and EA remain static during message processing. The
third word in the descriptor block identifies the current
address CA (i.e., last accessed address plus one). The
Descriptor Word 1
Descriptor Word 2
Descriptor Word 3
Descriptor Word 4
Control Word
SA (Buffer Start Address)
CA (Buffer Current Address)
EA (Buffer End Address)
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
199
circular buffer wraps to the start address after complet-
ing a message that results in CA being greater than or
equal to EA. If CA increments past EA during message
processing, the device will access memory addresses
greater than the EA value. Reserve 33 address locations
past the EA address to accommodate a worst-case 32
data word message with a record starting at address =
EA minus 1.
Each receive subaddress and transmit subaddress may
have a unique circular buffer assignment. The RT de-
codes the command word T/R bit, subaddress field and
word count / mode code field to select the unique com-
mand descriptor block containing the Control Word, SA
pointer, CA pointer and EA pointer.
For receive messages, the device stores the Message
Information word to the address specified by CA, the
Time-Tag word into CA+1 and the data into the next “N”
locations starting with CA+2. For transmit messages, the
device stores the Message Information word to the ad-
dress specified by CA and the Time-Tag word into CA+1.
Retrieval of data for transmission starts at address
CA+2. When entering multiple transmit command data
packets into the circular buffer, delimit each data packet
with two reserved memory locations. The device stores
the Message Information word and Time-Tag word into
the reserved locations when processing the command.
Message processing for all commands begins with the
device reading the unique descriptor block for the sub-
address or mode code specified by the T/R bit, subad-
dress and word count fields in the received command
word.
For receive messages, the device stores “N” received
data words in the circular data buffer. The first data word
received is stored at the location specified by the CA
pointer +2. After message completion, the device stores
the Message Information word and Time-Tag words to
addresses CA and CA+1 respectively. If no errors were
detected, the device updates descriptor CA register. If
the next address location (last stored data word +1) is
less than or equal to EA, CA is updated to (last stored
address +1). If the next address location (last stored
data word +1) is greater than EA, the data buffer is full
(or empty); CA is updated to the SA value. If descriptor
Control Word IXEQZ bit is asserted (and if Interrupt En-
able Register IXEQZ bit is asserted) the device gener-
ates an interrupt to indicate full receive buffer by assert-
ing the INTMES interrupt output.
Although all messages store Message Information and
Time-Tag words, no data is stored if the message end-
ed with error, or if the Busy status bit was set or if the
commend was illegal (example: illegalized word count).