hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 43

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Here is a summary of host-initiated operations involving the MT time tag counter:
Host interrupts can be generated when any of the four time tag counters in the device reach preset values contained
in Time Tag Match registers. Refer to the Interrupt Management section of the data sheet.
9.7.
This 16-bit read-write register is cleared after MR pin master reset, but is unaffected by assertion of MTRESET,
RT1RESET or RT2RESET register bits.
When written, register bits 15-8 work in pairs to initiate a particular action, such as clearing or loading one of these
counters. When written, register bits 15-8 self reset to zero after initiating the assigned action. Thus, bits 15-8 always
read logic 0. Register bits 7-0 are used for configuring the various time tag counters in the HI-613x device. These
bits will read back the last value written by the host.
15 14 13 12 11 10
0
a. Clearing a 16- or 48-bit MT time tag count, whichever is enabled.
b. When 16-bit MT time tag count is enabled,
c. When 48-bit MT time tag count is enabled,
0
•
•
•
•
Time Tag Counter Configuration Register (0x0039)
0
loading the 16-bit MT time tag counter with the 16-bit value contained in the MT TT16 Time Tag Utility
Register
capturing the current 16-bit MT time tag counter value to the MT TT16 Time Tag Utility Register
loading the 48-bit MT time tag counter with the 48-bit value contained in the MT TT48 Time Tag Utility
Register triplet
capturing the current 48-bit MT time tag counter value to the MT TT48 Time Tag Utility Register triplet when
48-bit MT time tag count is enabled
0
0
0
0
9
0
8
RW
7
0
0
6
0
5
4
0
0
3
HOLT INTEGRATED CIRCUITS
0
2
HI-6130, HI-6131
0
1
0
0
MR Reset
Host Access
Bit
43