hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 221

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

24. HOST INTERFACE
24.1. HI-6130 Host Bus Interface
The HI-6130 uses a parallel bus interface for
communications with the host. Host interface to
registers and RAM is enabled through the Chip Enable
(CE) pin, and accessed via 16-bit data bus and several
host-originated control signals described below. Timing
is identical for register operations and RAM operations
via the host bus interface, but read and write operations
have different signal timing. The HI-6130 parallel host
bus interface is capable of faster communication than
the HI-6131 Serial Peripheral Interface.
Depending on the chosen microprocessor family, the
processor’s hardware bus interface may be described
as an “external bus interface,” “memory interface” or
may have a different name. The user can also imple-
ment a software controlled “bit-banged” interface to the
HI-6130, at the cost of substantially slower RAM and
register read/write times.
The bus interface is compatible with the two prevalent
bus control signal methods: “Intel style” interface, char-
acterized by separate strobes for read and write opera-
tions (OE and WE), and “Motorola style” interface, char-
acterized by a single read/write strobe (STR) and a data
direction signal (R/W). Bus control style is selected us-
ing the BTYPE configuration pin, which sets the function
of two other input pins to serve as either OE and WE, or
STR and R/W.
The BWID configuration pin selects either 8- or 16-bit
bus widths. When the BWID pin is connected to ground,
8-bit mode is selected; two bytes are sequentially trans-
ferred for each 16-bit word operation. In 8-bit mode only,
the BENDI configuration pin selects bus “endianness.”
This is the system attribute that indicates whether in-
tegers are represented with the most significant byte
stored at the lowest address (big endian) or at the high-
est address (little endian). Internal device storage is “big
endian”. For processor compatibility, the BENDI pin sets
the order for byte accesses when the host bus is config-
ured for 8-bit width, that is, when BWID equals 0. When
BENDI is low, “little endian” is chosen; the low order byte
(bits 7:0) is transacted before the high order byte (bits
15:8). When BENDI is high, “big endian” is chosen and
the high order byte is transacted on the host bus before
the low order byte. In 8-bit mode, all transacted data
uses bus data bits 7:0 and bus data bits 15:8 are not
used. Further, bus address bit A0 (LB) always equals 0
during the first byte read/write access, and equals 1 dur-
ing the second byte access
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
221
When the BWID pin is connected high or left unconnect-
ed, 16-bit bus width is used. For 16-bit bus operation,
the A0 (LB) address pin is not used and the BENDI input
pin is “don’t care.”
24.1.1. Bus Wait States and Data Prefetch
The HI-6130 has a WAIT output pin that tells the host to
add wait states when additional access time is needed
during bus read cycles. For compatibility with different
host processors, the state of the WPOL input pin sets
the WAIT output as active high or active low. The WAIT
output can be ignored when the host processor read
cycle time is always slow enough to work with the HI-
6130 bus. When using fast host processors, cycle time
is sometimes slowed down by configuring the processor
to add one or more wait states during every read or
write cycle, but slow-down affects all cycles, even when
unnecessary.
Data prefetch is a technique used by the HI-6130 to
speed up host multi-word read access to registers or
RAM by eliminating wait states. Prefetching occurs
when HI-6130 logic requests data before it is actually
needed. Because register or RAM locations are often
read sequentially, performance improves when data is
prefetched in address sequence order. For every host
read cycle, the device first reads the addressed loca-
tion, then prefetches the following address, to speed up
access in the likely event that the following word will be
read next.
For the HI-6130, WAIT is always asserted for the first
word fetched in any read sequence. The first read cycle
has a long access time because there is no prefetch.
This may be the first byte read in 8-bit mode, or the first
word read in 16-bit mode. After each word (or byte) is
fetched for a read operation, the next word (or byte)
is prefetched to speed-up the read cycle time when
sequential address read sequences occur. After the first
word read, the following words read in sequence are
accessed without WAIT, resulting in faster overall multi-
word read timing. As long as bytes or words are read in
address order, additional wait states are unnecessary.
Data prefetch during read cycles is blocked when the
next RAM address is a Control Word in the Descrip-
tor Table. The table base address (set by the value in
register 0x0005) and every fourth word thereafter is a
Control Word. This consists of table addresses having
these address offsets from the table start address of 0,
4, 8, 0xC… 0x1F8 and 0x1FC. If allowed, prefetch (like
any other read) would reset the Control Word DBAC sta-
tus bit, so prefetch is disallowed in this range. Thus for
HI-6130, multi-word sequential read sequences will
assert WAIT every fourth word when reading RAM