hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 49

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

10. BUS CONTROLLER − CONFIGURATION AND OPERATION
The HI-613x can operate as an autonomous MIL-STD-1553 Bus Controller (BC), requiring minimal host processor
support. All MIL-STD-1553B error-checking is automatically performed, including RT response time, Manchester II
encoding, sync type, bit count, word parity, word count, responding RT address, and detection of the full range of pos-
sible error conditions encountered during BC operation. The device implements all MIL-STD-1553B message formats.
Message format is configurable on a message by message basis. Each message is individually programmable for
command type. Individual messages can be programmed for automatic retries on either bus, and interrupt requests
may be enabled or disabled.
The HI-613x Bus Controller provides a flexible means for scheduling major and minor frames, allowing insertion of
asynchronous messages during frame execution. Upon error, individual messages can be programmed for one or two
automatic retries, and the BC can switch buses before retry occurs. Message data is separated from control and status
data, to serve the needs for double buffering in RAM and bulk data transfers.
Before Bus Controller operation can begin, the BCENA input pin must be connected to logic 1 to allow BC operation. All
Bus Controller operational registers (see Section 11) must be properly configured. The BC Instruction List in RAM must
be initialized to define message sequencing and conditional execution, and finally the host must assert BCSTRT bit
13 in the Master Configuration Register 0x0000 to initiate execution of Instruction List op codes. The following pages
provide the necessary details for successful Bus Controller operation.
Figure 3 shows the registers and RAM resources utilized by the Bus Controller. All Bus Controller registers are fully
described in Section 11.
Initial control of BC message sequencing involves the BC Instruction List Pointer in register 0x0034. Before BC
execution begins, the instruction list starting address is copied from the BC Instruction List Start Address Register,
0x0033. Once message sequencing is underway, the BC Instruction List Pointer in register 0x0034 is updated by the
BC control logic.
The BC Instruction List in RAM comprises a series of 2-word entries, an instruction op code followed by a parameter
word. While processing messages, the BC control logic fetches and executes the instruction op code referenced by
the BC Instruction List Pointer from the BC Instruction List. The pointer parameter, referencing the first word in the
Message Control/Status Block, must have the form 0xHHH8 or 0xHHH0, where each H represents a hex character,
0-9 or A-F. If the individual message is RT-to-RT, the address must have the form 0xHHH0.
Each op code word in the BC Instruction List has the format:
Bus Controller execution stops immediately if the BC logic fetches an op code word having one or more of these error
conditions:
If enabled in the BC Interrupt Enable Register 0x0010, a BCTRAP interrupt occurs when execution stops because of
an illegal op code.
•
•
•
Parity
Odd
15 14 13 12 11 10
X
P
Bit 15 contains even parity
Bits 14-10 contain an undefined op code
Validation field bits 9-5 do not equal 01010
X
Op Code Field
X
X
X
X
0
9
Validation Field
1
8
7
0
1
6
0
5
4
X
Condition Code
HOLT INTEGRATED CIRCUITS
X
3
X
HI-6130, HI-6131
2
X
1
X
0
Bit
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