hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 125

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

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Initialized values for registers 0x002A – 0x002D may result in multiple small packets occurring within the Stack
address range. If registers 0x002A through 0x002D all contain zero, data packet finalization defaults to “imminent
buffer overrun” mode. Each data packet created will be slightly less than the allocated Stack address range. Suc-
cessive IRIG-106 data packets are written in circular buffer fashion. Each new data packet starts one word after
the final word in the previously finalized data packet.
If the first data packet after reset begins at the Stack Start Address, it will be finalized and the second data packet
will begin before reaching the Stack End Address boundary.
Last-Written Block Status Word Address is updated by the device each time a Block Status Word is added to the
end of the packet for a newly received MIL-STD-1553 message.
Two optional stack interrupts are offered. When enabled, the Stack Address Interrupt occurs whenever the match-
ing RAM address in the Stack is written. This address is fixed with respect to the Stack Start and End Addresses.
When enabled, the Packet Fill Warning Interrupt is generated when the packet length reaches a specified num-
ber of words before Packet Start Address overwrite occurs. Because Packet Start Address “walks” through the
stack address range for successive packets, the interrupt logic adjusts the Packet Fill Warning Interrupt address
automatically. The fill warning number can be any value, i.e. half-way, 8,192 for a 16,384-word buffer. Used in
conjunction with the Packet Ready interrupt, this packet “half full” setting produces alternating interrupts at the
“half full” and “full” packet conditions. To prevent packet start address overwrite, these two interrupts tell the host
when to offload data, a half packet at a time. In the event that the host is unable to immediately service a Packet
Ready interrupt, no data is lost when the IMT is configured to immediately start a new packet upon completion of
the prior packet (i.e., when PKTMR bit 7 equals logic 1 in the IMT Configuration Register 0x0029).
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
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