hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 227

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

the buffer for each interrupt, the Interrupt Log Address
register always contains an even value in the range of
0x0180 to 0x01BE.
When servicing an interrupt that just occurred, the host
wants timely information on that interrupt. An SPI com-
mand is provided to simplify interrupt handling:
Note: Bits 15:9 in the Interrupt Log Address register con-
tain the interrupt count since the Log Address register
was last read. These bits are not written to the Memory
Address Pointer.
This command can be used to read a single location (the
last-written Interrupt Address Word), or may be used to
start a multi-word read in which the Memory Address
Pointer automatically decrements after each word is
read, reading words stored in the Interrupt Log Buffer, in
Last In First Out order. This is the only SPI op code that
decrements the Memory Address Pointer for multi-word
operations. Repeated memory pointer decrements will
wrap around the 0x0180 to 0x01BF Interrupt Log Buffer
boundary.
Notice: There is no MAP auto-increment or data prefetch when MAP equals 0x0403, so the final two read cycles re-
peat the previous read value and address.
FROM
HOST
===== ======= ==========================================
0xD8
0x8B
0x0400 ---- RT1 Descriptor Table start address written to MAP.
0x40
---- <data> data from 0x0400 (SCK continues afterward)
---- <data> data from 0x0401 (SCK continues afterward)
---- <data> data from 0x0402 (SCK continues afterward)
Command Read Operation
0x58
FROM
HI-6131
---- SPI op enables memory address pointer (MAP) 0x000B.
---- SPI op code writes memory address pointer (MAP).
---- SPI op code to “read location addressed by MAP”
Write enabled Memory Address Pointer
with the current bit 8:0 address value
in Interrupt Log Address register minus
1. (See note.) If address bits 8:0 equal
0x0180, then 0x1BF is written into Mem-
ory Address Pointer. Then read the new-
ly-addressed RAM location, containing
the last-written Interrupt Address Word.
Then decrement the Memory Address
Pointer, which then addresses the cor-
responding Interrupt Information Word
COMMENT
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
227
24.2.8. RT Descriptor Table Prefetch
For the SPI-interface HI-6131, the enabled Memory Ad-
dress Pointer (register 0x000F) contains the address for
each new word read by the host. When starting a read
access, the host usually writes the enabled Memory Ad-
dress Pointer with the address for the first word to read.
The host then uses an SPI op code to initiate the read
process. After the addressed word is transferred by SPI
to the host, the HI-6131 continues to read and trans-
mit words from sequential RAM memory addresses, as
long as the host continuously asserts chip select while
providing SCK serial clock pulses. After fetching each
new word, the device increments the Memory Address
Pointer and prefetches the data contained in the newly
addressed location. The next word is prefetched even
when the host does not ultimately read the following ad-
dress. For HI-6131, sequential reads from the RT1 or
RT2 Descriptor Table that rely on MAP auto-increment
will stop advancing when the next address contains a
RT Descriptor Table Control Word. Properly designed
SPI transfers overcome this behavior.
Using SPI command op codes, the HI-6131 host must
consider prefetch and pointer behavior when reading
data from the Descriptor Table. Applied outside the RT
Descriptor Table, the following SPI sequence would read
data from six successive memory addresses. But below,
applied within the table, the sequence gets stuck at the
fourth word read.
Below we assume the RT1 Descriptor Table starts at de-
fault base address, 0x0400. The host first uses SPI op
codes 0xD8 and 0x8B to enable Memory Address Point-
er 0x000B then write the table start address 0x0400 into
it. The sequence then uses op code 0x40 (and MAP au-
to-increment) to read the first MAP-addressed location
and successive locations.
Exceptions