hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 171

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Bit No. Mnemonic R/W Reset Function
14
13
12
11
10
9
IWA
IBR
MKBUSY
DBAC
DPB
BCAST
SR = 0
SR = 0
SR = 0
0
0
0
0
0
0
Interrupt When Accessed.
If the Interrupt Enable Register IWA bit is high, assertion of this bit enables
interrupt generation when the subaddress receives any valid receive com-
mand. If enabled, upon completion of command processing, an IWA interrupt
is entered in the Pending Interrupt Register, output pin INTMES is asserted,
and the interrupt is registered in the Interrupt Log.
Interrupt Broadcast Received.
If the Interrupt Enable Register IBR bit is high, assertion of this bit enables
interrupt generation when the subaddress receives a valid broadcast com-
mand. If enabled, upon completion of message processing an IBR interrupt is
entered in the Pending Interrupt Register, output pin INTMES is asserted, and
the interrupt is registered in the Interrupt Log. This bit has no function if the
BCSTINV bit is high in Configuration Register 1. In this case, commands to RT
address 31 are not recognized as valid by the device.
Make Busy.
The host asserts the MKBUSY bit to respond with Busy status for commands
to this receive subaddress. This bit is an alternative to globally applying Busy
status for all valid commands, enabled from the 1553 Status Bits Register.
See that register description for additional information. When Busy is asserted,
received data words are not stored and the DPB bit does not toggle after mes-
sage completion.
Descriptor Block Accessed.
Internal device logic asserts the DBAC bit upon completion of message
processing. The host may poll this bit to detect subaddress activity, instead
of using host interrupts. This bit is reset to logic 0 by MR master reset, SRST
software reset or a read cycle to this memory address.
Data Pointer B.
This status bit is maintained by the device and only applies in ping-pong buffer
mode. This bit indicates the buffer to be used for the next occurring receive
command to this subaddress. When the DPB bit is logic 0, the next message
will use Data Pointer A; when DPB is logic 1, the next message uses Data
Pointer B. In ping-pong buffer mode, the bit is inverted after each error-free
message completion. The DPB bit is not altered after messages ending in er-
ror, after illegal commands or after messages when the terminal responds with
Busy status. This bit is reset to logic 0 by MR master reset or SRST software
reset; therefore the first message received after either reset will use Buffer A.
This bit is “don’t care” for indexed single-buffer mode or either circular buffer
mode.
Broadcast Command.
Device logic sets this bit when a valid broadcast receive command is received
at this subaddress. If IBR bit 13 and Interrupt Enable Register IBR bit are both
set, the output pin INTMES is asserted. This bit has no function if the BCST-
INV bit is asserted in the Configuration Register 1; in this case commands to
RT address 31 are not recognized as valid by the device. This bit is reset to
logic 0 by MR master reset or SRST software reset.
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
171