hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 147

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

18.4. Remote Terminal 1 (RT1) Current Control Word Address Register (0x0003)
These 16-bit registers are read-only and are fully maintained by the device. These registers are cleared after MR pin
master reset, but are unaffected by assertion of RTxRESET remote terminal software reset in the Master Status and
Reset Register (0x0001).
These registers contain the address for the descriptor table Control Word corresponding to the current command
stored in the Current Command Register, above. These registers are updated 5 µs after the ACTIVE output is as-
serted for recognition of a valid command for the RT. Also see description for the “Current Message Information Word
Address” register.
18.5. Remote Terminal 1 (RT1) Descriptor Table Base Address Register (0x0019)
These 16-bit registers are Read-Write and contain the starting address for the Remote Terminal’s Descriptor Table.
These registers are initialized with default values after MR pin master reset, or by assertion of RTxRESET remote
terminal software reset in the Master Status and Reset Register (0x0001). For RT1, the post-reset register value is
0x0200. For RT2, the post-reset register value is 0x0400. After initialization, these registers are fully maintained by
the host. Bit 15 and bits 8:0 cannot be set and will always read logic 0.
MSB
MSB
MSB
15 14 13 12 11 10 9
15 14 13 12 11 10 9
15 14 13 12 11 10
R
R
0
0
0
0
0
0
Remote Terminal 2 (RT2) Current Control Word Address Register (0x0005)
Remote Terminal 2 (RT2) Descriptor Table Base Address Register (0x0022)
0
0
0
0
0
0
RW
RW
Register Address 0x0019 (RT1)
Register Address 0x0019 (RT1)
0
0
0
0
0
1
Register Value
Register Value
Register Value
1
0
0
9
8
8
0
8
0
0
R
7
7
7
0
0
0
0
6
0
6
0
6
0
0
0
5
5
5
4
R
4
R
4
0
0
0
0
3
0
3
0
3
HOLT INTEGRATED CIRCUITS
0
0
0
2
2
2
HI-6130, HI-6131
0
1
0
1
0
1
LSB
LSB
LSB
0
0
0
0
0
0
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
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