hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 16

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

3. PIN DESCRIPTIONS
Pin
MCLK
TTCLK
MTTCLK
MR
TXINHA
TXINHB
MTSTOFF
AUTOEN
READY
ACTIVE
ECS
ESCK
MOSI
MISO
EECOPY
BCENA
Function
Input
50KΩ pull-down
Inputs
50KΩ pull-down
Input
50KΩ pull-up
Inputs
50KΩ pull-down
Input
50KΩ pull-down
Input
50KΩ pull-down
Output
Output
Output
Output
Output
Input
50KΩ pull-down
Input
50KΩ pull-down
Input
50KΩ pull-down
Table 1. Common pins (Apply to both HI-6130 and HI-6131)
Description
Master clock input, 50.0MHz +/-100 ppm.
Optional clock input for BC time base and RT time tag counters.
Optional clock input for the MT time tag counter.
Each function (BC, MT, RT1, RT2) has an independent time tag counter. The BC
and RT counters share a common clock, selectable from internally generated
frequencies, or an external clock input. The MT time tag counter has its own
external or internal clock source.
Master reset, active low. The host can also assert software reset by setting bits
in the Master Status & Reset register.
Transmit inhibit inputs for Bus A and Bus B, active high. These two inputs are
logically ORed with the pair of corresponding bits in the Master Configuration
Register to enable or inhibit transmit on Bus A or Bus B, affecting behavior for
all enabled 1553 devices.
Memory test disable, active high. When this pin is low, the device performs a
memory test on the entire RAM after rising edge on the MR reset pin. When this
pin is high, RAM testing is skipped, resulting in a faster reset process. For further
information, refer to the data sheet section entitled “Reset and Initialization.”
Auto-Initialize Enable, active high. If this pin is high at rising edge on MR reset
pin, self-initialization proceeds, copying configuration data to registers and RAM
from an external serial EEPROM via a dedicated EEPROM SPl port. Refer to
the data sheet section entitled “Reset and Initialization.”
This pin is low when auto-initialization or built-in test is in process. The host
cannot read or write device RAM or registers when pin state is low; reads to
any address return the value in the Master Status & Reset register. When the
AUTOEN pin is low at Master Reset, the host can configure device RAM and
registers after READY goes high.
This pin is high while an enabled BC or RT in the device is processing a 1553
message. The IMTA bit 1 in Master Configuration Register 0x0000 logically-
ORs bus monitor (MT) activity as well.
Dedicated 4-wire Serial Peripheral Interface (SPI) for connection to an optional
external EEPROM used for automatic self-initialization when AUTOEN is high
at Master Reset.
EEPROM Copy, active high. Asserting this input initiates RAM and register copy
into serial EEPROM used for auto-initialization. Refer to the data sheet section
entitled “Reset and Initialization.”
Bus Controller Enable input, active high.
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
16