hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 154

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

18.14. RT1 and RT2 Remote Terminal Interrupt Registers and Their Use
Thirteen HI-613x registers are used for host interrupt management. In addition to the Interrupt Count & Log Address
Register described in Section 9.4, there are four 3-register groups, separated by function. One register group is for
Hardware interrupts, plus one register group each for Bus Controller, Bus Monitor and Remote Terminal interrupts. The
Remote Terminal register set is shared between RT1 and RT2. Each group (Hardware, BC, MT or RT) has
Each individual bit in all three registers is mapped to the same interrupt-causing event when the corresponding interrupt
condition is enabled. Numerous interrupt options are available for the RT. At initialization, bits must be set in the RT
Interrupt Enable register to identify the interrupt-causing events for the RT which are heeded by the HI-613x. Most
Monitor applications only use A subset of available RT interrupt options. Interrupt-causing events are ignored when
their corresponding bits are reset in the RT Interrupt Enable Register. Setting an Interrupt Enable register bit from 0 to
1 does not trigger interrupt recognition for events that occurred while the bit was zero.
Whenever an enabled monitor interrupt event occurs, the Interrupt Log Buffer is updated and a bit is set in the RT
Pending Interrupt Register. This action takes place only when the corresponding bit is already set in the RT Interrupt
Enable Register. The host can poll the RT Pending Interrupt Register to detect the occurrence of Monitor interrupts,
indicated by non-zero value. When the host reads the RT Pending Interrupt Register, it automatically clears to 0x0000.
When an enabled interrupt condition occurs and the corresponding bit is also set in the RT Interrupt Output Enable
Register, the IRQ output is asserted to alert the host. Thus, the RT Interrupt Output Enable Register establishes
two interrupt priority levels for the Monitor: high priority interrupts generate an IRQ signal output, while low priority
interrupts do not. The host detects low priority interrupts by polling the RT Pending Interrupt Register.
A single IRQ host interrupt output signal is shared by all enabled interrupt conditions having bits set in the four Interrupt
Output Enable registers. Multiple interrupt-causing events can occur simultaneously, so each IRQ output assertion can
result from one or several interrupt conditions.
When the host receives an IRQ signal from the device, it must identify the event (or events) that triggered the interrupt.
A hardware-assisted interrupt-decoding scheme simplifies interrupt identification. This scheme uses the three low
order bits in the Hardware Pending Interrupt Register.
Upon IRQ interrupt assertion, the host first reads the Hardware Pending Interrupt Register. Bits 15-3 in this register
identify hardware interrupt conditions. The three low-order bits the Hardware Pending Interrupt Register indicate zero
vs. non-zero status for the RT, MT and BC Pending Interrupt Registers. If any of these bits is logic 1, the corresponding
Pending Interrupt Register has one or more interrupt flags set. Any combination of these 3 bits may be set. Each of
the four Pending Interrupt registers self-resets to 0x0000 after the host reads its value. Thus, the host should retain
the value read from the Hardware Pending Interrupt Register when 2 or more bits are non-zero in the bit 2-0 range.
When MTIP (MT Interrupt Pending) bit 1 is set in the Hardware Pending Interrupt Register, the RT Pending Interrupt
Register contains a nonzero value, so should be read next to identify the specific RT interrupt event.
When polling the Pending Interrupt registers to identify low priority interrupts that do not assert the IRQ output, the
same method can be applied. At a single read of the Hardware Pending Interrupt Register reveals zero / non-zero
status of all four Pending Interrupt registers.
To help the host process interrupts, the HI-613x device maintains information from the 32 most recent interrupts in a
64-word ring buffer in RAM, located at the fixed address range 0x0180 to 0x01BF. Each interrupt stores two information
words: the Interrupt Identification Word (IIW) identifies the interrupt type(s) that occurred; the Interrupt Address Word
(IAW) identifies the interrupt source. For RT interrupts, the IAW contains a 16-bit address in the RT1 or RT2 Descriptor
Table, pointing to the Command Word used in the message in which the interrupt occurred.
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An Interrupt Enable Register to enable and disable interrupts
A Pending Interrupt Register to capture the occurrence of enabled interrupts
An Interrupt Output Enable Register to enable IRQ output to host, for pending enabled interrupts
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
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