hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 139

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Bit No.
15
14
13
12
10
11
9
8
7
6
5
4
3
Mnemonic
IRIGOVF
MAXWRDS
MAXMSGS
MAXGAP
MAXTIME
HPSTOP
PKTRDY
Reserved
Reserved
STKMAT
PKTFW
Reserved
Reserved
Function
IRIG-106 Stack Overflow.
Since start-of-packet, data recording got within 64 words of overwriting the Packet Start
Address. The in-process packet terminated at end-of-message. Next message begins
next packet.
IRIG-106 Maximum MIL-STD-1553 Word Count Interrupt.
The in-process packet terminated at end-of-message when the number of MIL-
STD-1553 message words recorded in the packet attained the maximum word count
stored in the MT Packet Maximum MIL-STD-1553 Word Count Register at address
0x002B.
IRIG-106 Maximum Message Count Interrupt.
The in-process packet terminated at end-of-message when the number of recorded
MIL-STD-1553 messages equals the maximum message count stored in the IMT
Packet Maximum Message Count Register at address 0x002A.
IRIG-106 Maximum Gap Time Exceeded Interrupt.
The in-process packet terminated when the bus monitor encountered a MIL-STD-1553
message gap interval exceeding the maximum gap time stored in the MT Packet
Maximum Gap Time Register at address 0x002D.
IRIG-106 Maximum Recording Time Exceeded Interrupt.
The in-process packet terminated when the bus monitor reached the maximum packet
time stored in the MT Maximum Packet Time Register at address 0x002C. When
timeout occurs, packet finalization occurs after completion of an unfinished message.
Host Packet Stop Interrupt.
The host asserted the PKSTOP bit in the MT Configuration Register to stop the bus
monitor. Recording stopped after in-process message completion.
Packet Ready Interrupt.
Above register bits 15-10 are logically ORed to derive the state of this bit.
This bit is not used in IMT monitor mode. It should be initialized logic 0 in the IMT
Interrupt Enable Register.
This bit is not used in IMT monitor mode. It should be initialized logic 0 in the IMT
Interrupt Enable Register.
Stack Address Match Interrupt.
The stack pointer value has reached the interrupt address in Word 3 of the IMT Address
List.
Packet Fill Warning Interrupt.
Host previously initialized Word 7 in the IMT Address List with a word count value, N.
The current stack pointer address has reached N words before overwriting the Current
Packet Start Address stored in Word 1 of the IMT Address List.
This bit is not used in IMT monitor mode. It should be initialized logic 0 in the IMT
Interrupt Enable Register.
This bit is not used in IMT monitor mode. It should be initialized logic 0 in the IMT
Interrupt Enable Register.
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
139