hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 225

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Three single-byte SPI commands modify the value in
the active Memory Address Pointer, selected by MAP-
SEL bits 11-10 in the Master Configuration Register:
The “Add 4” command may be useful when sequential-
ly accessing the same word (for example, the Control
Word) in a series of 4-word Descriptor Table entries. The
“Add 2” command might be useful for reading the Inter-
rupt Log Buffer, comprised of 2-word log entries. In both
cases, the Add command would be probably followed
by Read command 0x40 to read the location addressed
by the current pointer value. Similarly, Write command
0xC0 writes the location addressed by the current point-
er value. Two command bytes cannot be “chained”; the
host SPI Slave Select CE must be negated after the Add
command, then reasserted for the following Read or
Write command.
The active Memory Address Pointer is not affected by
fast-access read/writes to the low register addresses
because fast-access SPI commands use a separate, in-
ternal pointer not directly accessible to the host.
Two single-byte SPI commands use the current value of
the enabled Memory Address Pointer without first load-
ing or otherwise modifying it:
Either of these commands can be used to read or write
a single location, or may be used to start a multi-word
read or write that uses the MAP pointer’s auto-increment
feature.
One single-byte SPI command increment the current
value of the enabled Memory Address Pointer, then per-
forms a write:
Command Write Operation
Command Address Pointer Operation
Command Read Operation
0xC0
0xD0
0xD2
0xD4
0x40
write location addressed by enabled
Memory Address Pointer
increment enabled Memory Address
Pointer value
add 2 to enabled Memory Address
Pointer value
add 4 to enabled Memory Address
Pointer value
read location addressed by enabled
Memory Address Pointer
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
225
24.2.6. Data Prefetch for SPI Read Cycles
Data prefetch is a technique used by the HI-6131 to
speed up host multi-word read access to registers or
RAM. Prefetching occurs when HI-6131 logic accesses
data before it is actually needed. Because register or
RAM locations are often read sequentially, performance
improves when data is prefetched in address sequence
order. For any SPI read cycle, the HI-6131 first fetches
the addressed location, then increments the memory
address pointer and prefetches the following address,
to speed up access in the likely event that the follow-
ing word will be read next. For the HI-6131, read cycle
prefetch allows the SPI host to read sequential locations
back-to-back, continuing as long as the host asserts
chip select and provides SPI clock. This is described as
the Memory Address Pointer “auto-increment” feature.
There is an exception: read cycle prefetch is blocked
when the next RAM address is a Control Word in the
RT1 or RT2 Descriptor Table. If allowed, pre-fetch (like
any other read) resets the Control Word DBAC status
bit. To preserve DBAC status bit function, prefetch is
disabled when reading Control Words within Descriptor
Table address range. The table base address (set by the
value in register 0x0019 for RT1 or register 0x0022 for
RT2) and every fourth word thereafter is a Control Word.
This consists of table addresses having these offsets
from the table start address: 0, 4, 8, 0xC through and
including 0x1F8 and 0x1FC. See further information in
Section 24.2.8.
These two commands can be used to read or write a
single location, or may be used to start a multi-word read
or write that uses the pointer’s auto-increment feature.
24.2.7. Special Purpose Commands
Several other HI-6131 SPI commands load or otherwise
modify the active Memory Address Pointer before initiat-
ing a read or write process. These commands were tai-
lored to the specific needs of HI-6131 Remote Terminal
host software.
Using a single-byte SPI command, the active Memory
Address Pointer can be directly loaded with the mem-
ory address for the RT1 or RT2 descriptor table Con-
trol Word corresponding to the last completed MIL-
STD-1553 command. The Control Word is then read.
Command Write Operation
0xC8
add 1 to enabled Memory Address
Pointer then write addressed location