hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 165

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

19.3. Temporary Receive Data Buffer
The 32-word temporary receive data buffer resides in
shared RAM in address space 0x0020 to 0x003F. The
device optionally uses this buffer for temporary storage
of receive data words until successful message comple-
tion. To enable the buffer, the host asserts the TRXDC
bit in Configuration Register 2.
When enabled, the terminal stores received data words
in the 32-word buffer during message processing. Upon
error-free message completion, all buffered words are
written in a burst to the data buffer memory assigned to
the specific subaddress in the Descriptor Table.
When the TRXDB bit in Configuration Register 2 is ne-
gated, the temporary receive data buffer is disabled. At
20us intervals, the terminal writes received data words
to assigned subaddress data buffer memory as each
word is received. If message error occurs during data
reception, data integrity is lost; valid data from the prior
receive message may be partially overwritten by data
from a message ending in error. MIL-STD-1553 states
that all received data from messages ending in error
should be disregarded.
In a typical application, the temporary buffer is not di-
rectly accessed by the host, although there is no restric-
tion preventing host data access. The host should never
write data into the temporary buffer space.
19.4. Interrupt Log Buffer
Two interrupt output pins notify the host upon occur-
rence of pre-determined interrupt-causing events. The
interrupt types are listed below. Each interrupt type only
occurs when the corresponding interrupt type bit is as-
serted in the Interrupt Enable Register. To manage host
interrupts, the device architecture uses an Interrupt Log
buffer, three control registers, two interrupt output pins
and two interrupt acknowledge input pins. The data
sheet section entitled “Interrupt Management” provides
additional details.
Shown in Figure 15, the Interrupt Log Buffer is a 32-
word ring buffer located in shared RAM, at address
range 0x0040 to 0x005F. To help the host process inter-
rupts, the device interrupt manager maintains informa-
tion from the 16 most recent interrupts in this buffer. The
buffer contains two information words for each occurring
interrupt: the Interrupt Identification Word and Interrupt
Address Word.
The Interrupt Identification Word (IIW) identifies the oc-
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
165
curring interrupt type using a word format identical to the
Pending Interrupt Register. Upon update, all bits except
the occurring interrupt type bit(s) are reset.
More than one bit may be asserted in an Interrupt Identi-
fication Word. For example, IBR (interrupt broadcast re-
ceived) and MERR (interrupt message error) can occur
for the same message. One assertion of the INTMES
output pin alerts the host when concurrent message in-
terrupts occur.
The Interrupt Address Word (IAW) identifies the origi-
nating command for message-based interrupts. When
interrupts originate from message processing, the Inter-
rupt Address Word (IAW) identifies the interrupt source
using the 16-bit address of the command’s Control Word
in the Descriptor Table. Hardware interrupts are not
linked with command processing. These interrupts write
an Interrupt Address Word value of 0x0000.
After MR reset or SRST software reset, the device auto-
matically initializes bits 7:0 in the Interrupt Log Address
IIW - Interrupt Information Word
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 14. Interrupt Information Word Bits
Interrupt
SPIFAIL
TTINT1
TTINT0
EECKF
RTAPF
ILCMD
RAMIF
IXEQZ
MERR
LBFB
LBFA
IWA
IBR
Summary
Hardware
Hardware
Hardware
Hardware
Hardware
Hardware
Hardware
Hardware
Message
Message
Message
Message
Message
Origin
-----
-----
-----
IAW contains 0x0000
IAW contains the
Command Word
Descriptor Table
IAW - Interrupt
Address Word
Address