hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 215

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

5. The EECOPY input pin is driven high for at least 1 ms, then driven low. In response, the READY output goes low
6. For terminal devices selected for auto-enable by step 4 unlock word selection, the RT1STEX, RT2STEX, MTENA
22.2. Overall 32K Checksum Used by Auto-Initialization
When auto-initialization is performed, the overall checksum (stored in EEPROM by the EECOPY process) is used
for error checking. EECOPY stored this checksum value in the two 8-bit locations corresponding to RAM address
0x004E. This checksum covers the entire 32K register and RAM address range from 0 to 0x7FFF, excluding the
following register addresses. At auto-initialization, the following registers are not written using EEPROM data:
The four terminals can be automatically started (or not started) in any combination. For example, exclusive-ORing
both default unlock Words 1 and 2 with 0x0FF0 results in unlock Word 1 = 0xAFFA and Word 2 = 0x5005. This
combination automatically and simultaneously enables execution for all four terminal devices: BC, MT, RT1 and
RT2, at every subsequent auto-initialization from EEPROM. Individual soft resets for a single terminal device will
automatically enable that device, if enabled here.
while EEPROM memory is written. The unlock code at address 0x004E is cleared. Device register and RAM con-
tents are written to the serial EEPROM, one byte at a time.
During programming, terminal checksums are tallied for the RT1, RT2 and SMT/IMT terminal devices, if used. An
overall 32K checksum is also tallied. These checksums, stored in the EEPROM, are used for error detection later,
during auto-initialization and soft reset events. There is no Bus Controller soft reset.
On the following pages, see the list of registers included in the stored overall and terminal checksums. When the
READY output goes high, EEPROM copy is complete.
and/or BCSTRT bits are set in the 2-byte EEPROM image corresponding to Master Configuration Register 0x0000.
During subsequent auto-initialization events, these are the last bits written, just before READY assertion. Terminal
devices having enable bits set to logic 1 in the EEPROM image are automatically and simultaneously enabled
just before READY assertion. Terminal devices not automatically enabled (by step 4 unlock word selection) have
logic 0 enable bits RT1STEX, RT2STEX, MTENA and/or BCSTRT in the 2-byte EEPROM image corresponding
to Master Configuration Register 0x0000. After auto-initialization, these terminal devices remain in standby until
enabled by host write to the Master Configuration Register 0x0000.
Table 19. Registers are not written using EEPROM data
SMT or IMT Checksum
Overall Checksum
Checksum Type
RT1 Checksum
RT2 Checksum
Address
0x000A
0x0002
0x0007
0x0008
0x0009
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
RT1 & RT2 Pending Interrupt Register
Master Status & Reset Register
BC Pending Interrupt Register
MT Pending Interrupt Register
Interrupt Log Address Pointer
215
Excluded Register Name
EEPROM location corresponds to
RAM Address
0x01C0
0x005C
0x004E
0x01E0