hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 126

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

16. REGISTERS USED BY THE IMT BUS MONITOR
In addition to the registers described here, a HI-6131 IMT Bus Monitor also utilizes one or more Memory Address
Pointer registers (described in Section 9.8) for managing SPI read/write operations. This comment does not apply for
parallel bus interface HI-6130 designs.
16.1. IMT Bus Monitor MT Configuration Register (0x0029)
15 − 14
15 14 13 12 11 10 9
Bit No.
0
RW
13
0
W
0
Mnemonic
MTTO1:0
PKTSTOP
0
0
0
0
0
8
R/W
R/W
W
7
0
RW
0
6
Reset
0
5
0
0
4
0
0
3
HOLT INTEGRATED CIRCUITS
Function
MT Time Out Select.
This 2-bit field selects the Monitor “no response” time-out delay from
four available selections. Excluding RT-RT commands, the delay is
measured from command word mid-parity bit to status word mid-sync.
For RT-RT commands, time out delay is measured per Figure 8 in the
RT Validation Test Plan, SAE AS4111. That is, from mid-parity of the
receive command to mid-sync of the first received data word. This adds
40µs for the embedded transmit command word and transmit-RT status
word within this interval.
MT Packet Stop.
If packet recording is underway when the PKTSTOP bit is set, the IMT
stops recording then post-processes the packet. If a MIL-STD-1553
message is underway when PKTSTOP is set, recording continues to
message completion. The IMT immediately begins recording a new
packet.
If packet recording is not underway, setting PKTSTOP has no effect.
This bit self-resets when written to logic 1. Writing logic 0 to this bit has
no effect.
Bit 15:14
0
2
HI-6130, HI-6131
00
01
10
11
0
1
0
0
MR Reset
Host Access
Bit
126
138μs
Dead
Time
16μs
21μs
80μs
Bus
Time Out (excludes
RT-RT)
140μs
18μs
23μs
82μs
RT-RT Time Out
122μs
180μs
61μs
66μs