hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 84

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

11.7. Bus Controller (BC) General Purpose Flag Register (Write 0x0037)
Sharing the same register address as the Read-Only BC Condition Code Register, this 16-bit register is Write-Only.
This register is written by the host to set, clear or toggle any combination of the 8 general-purpose flags 7-0 in the BC
Condition Code Register. When this register is written, general-purpose flags are modified. Reading register address
0x0037 returns the value in the BC Condition Code Register, containing the modified GP flag bits (see Section 11.6).
Each general-purpose flag in the BC Condition Code Register is mirrored twice in the General Purpose Flag Register,
once in the upper byte and once in the lower byte. Bits asserted in the lower byte set the corresponding GP flag bits
in the BC Condition Code Register to 1. Bits asserted in the upper byte clear the corresponding GP flag bits in the BC
Condition Code Register to 0. Bits asserted in both the lower and upper bytes for a specific GP flag toggles (inverts)
the corresponding GP flag bit in the BC Condition Code Register. When both bits are written to logic 0 state for a spe-
cific GP flag bit, no change occurs for that GP flag bit. The FLG instruction op code operates similarly, as shown in the
diagram in Figure 4.
11.8. Bus Controller (BC) General Purpose Queue Pointer Register (0x0038)
This 16-bit register is a combination of Read-Only and Read-Write bits. This register contains 0x00C0 after MR pin
master reset. The initialized value represents the base address for the 64-word BC General Purpose Queue. The host
can overwrite the default 0x00C0 value, but low order bits 5-0 and bit 15 must equal logic 0 for the initialized value.
These bits cannot be set to logic 1 by a host write cycle.
The general purpose queue provides a way for the Bus Controller message sequencer to convey various information
to the external host. The BC instruction set includes op codes that push data values onto this queue, including immedi-
ate data values, the Block Status Word from the most recent message, the Time Tag Register count, or the contents
of a specified memory address.
15 14 13 12 11 10 9
MSB
Bit No.
15 − 8
0
15 14 13 12 11 10 9
R
7 − 0
0
0
0
0
0
Mnemonic
CLEAR
GP7 − GP2
SET
GP7 − GP2
0
General Purpose Queue RAM Address
0
0
0
RW
0
0
0
0
0
8
8
0
W
R/W
W
W
7
0
7
1
0
6
1
6
Reset
0
5
0
5
0
0
4
0
4
0
0
3
0
3
HOLT INTEGRATED CIRCUITS
Function
Clear General Purpose Flag 7-0.
Bits asserted in the upper byte clear the corresponding GP flag bits in
the BC Condition Code Register to 0.
Set General Purpose Flag 7-0.
Bits asserted in the lower byte set the corresponding GP flag bits in the
BC Condition Code Register to 1. Bits asserted in both the lower and
upper bytes for GPx toggles that GP flag bit in the BC Condition Code
Register.
R
0
2
0
2
HI-6130, HI-6131
0
1
0
1
LSB
0
0
0
0
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
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