hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 170

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

19.5.1. Receive Subaddress Control Word
Receive Subaddress Control Words apply when a valid command word T/R bit equals zero (receive) and the subad-
dress field has a value in the range of 1 to 30 (0x1E). The descriptor Control Word defines terminal command response
and interrupt behavior, and conveys activity status to the host. It is initialized by the host before terminal execution
begins. Bits 8-11 cannot be written by the host; these bits are updated by the device during terminal execution, that
is, when Configuration Register 1 STEX bit equals 1. The host can write bits 0-2 and 4-7 only when STEX equals
zero; bits 3 and 12-15 can be written anytime. This register is cleared to 0x0000 by MR master reset. Software reset
(SRST) clears just the DBAC, DPB and BCAST bits. Following any read cycle to the Control Word address, the
DBAC bit is reset.
NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is un-
changed unless specifically indicated by an “SR” value.
Bit No. Mnemonic R/W Reset Function
MSB
15
Command
0 0 0 0 0 0 1
Sync
15 14 13 12 11 10 9
H
0x0
Figure 17. Deriving a Descriptor Table Control Word Address From Command Word
SA4:0 equals 00001 to 11110
for Subaddress Commands
IXEQZ
H
Descriptor Table Address
H
RT Addr
TA4:0
H
0x2
D1 D
0
T/
Bi
R
t
D
Subaddress
SA4:0
D
8
0
H
7
H
6
Interrupt When Index Equals Zero.
If the Interrupt Enable Register IXEQZ bit is high, assertion of this bit enables
generation of an interrupt for (a) subaddresses using indexed buffer mode
when the INDX value decrements from 1 to 0, or (b) subaddresses using a
circular buffer mode when the pre-determined number of messages has been
transacted. If enabled, upon completion of command processing that results in
index = 0, an IXEQZ interrupt is entered in the Pending Interrupt Register, out-
put pin INTMES is asserted, and the interrupt is registered in the Interrupt Log.
(assumes table base address = 0x0200)
0 0
Word Count
H
5
WC4:0
HOLT INTEGRATED CIRCUITS
H
4
Command Word’s Subaddress
Descriptor Address Format
HI-6130, HI-6131
H
3
H
2
P
Depends On
H
1
H
0
170
LSB
Command
Sync
D1
H
D
RT Addr
TA4:0
0 0 0 0 0 0 1
Bit maintained by host
Bit maintained by device
Bit set by device, reset by host read cycle
0x0
SA4:0 equals 00000 or 11111
T/
for Mode Code Commands
Bi
Descriptor Table Address
R
t
Subaddress
0x3
SA4:0
1
Mode Code
MC4:0
P
0 0