hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 180

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Bit No. Mnemonic RW
12
11
10
9
8
MKBUSY
DBAC
DPB
BCAST
PPON
Reset
SR = 0
SR = 0
SR = 0
0
0
0
0
0
Function
Make Busy.
The host asserts the MKBUSY bit to respond with Busy status for commands
to this mode code. This bit is an alternative to globally applying Busy status
for all valid commands, enabled from the 1553 Status Bits Register. See that
register description for additional information. When Busy is asserted, mode
data words are not transmitted with MC16-MC31, and the DPB bit does not
toggle after message completion. The MKBUSY bit is not heeded if set in the
Control Word for mode code command MC8 “reset remote terminal”. For this
command only, Busy is inhibited for the status response transmitted before
the reset process begins.
Descriptor Block Accessed.
Internal device logic asserts the DBAC bit upon completion of message pro-
cessing. The host may poll this bit to detect mode command activity, instead
of using host interrupts. This bit is reset to logic 0 by MR master reset, SRST
software reset or a read cycle to this memory address.
Data Pointer B.
This status bit is maintained by the device and only applies for mode com-
mands using ping-pong buffer mode. This bit indicates the buffer to be used
for the next occurring mode command. When the DPB bit is logic 0, the next
message will use Data Pointer A; when DPB is logic 1, the next message
uses Data Pointer B. In ping-pong buffer mode, the bit is inverted after each
error-free message completion. The DPB bit is not altered after messages
ending in error, after illegal commands, or after messages when the terminal
responds with Busy status. This bit is reset to logic 0 by MR master reset or
SRST software reset; therefore the first message received after either reset
will use Buffer A. This bit is “don’t care” for indexed single-buffer mode.
Broadcast Received.
Device logic sets this bit when a valid broadcast mode command is received
having T/R bit = 1. This bit has no function if the BCSTINV bit is asserted in
Configuration Register 1. In this case, RT address 31 commands are not rec-
ognized as valid by the HI-6130/21. This bit is reset to logic 0 by MR master
reset or SRST software reset.
Ping-Pong Enable Acknowledge.
This bit is read only and only applies for mode commands using ping-pong
mode (PPEN bit 2 was initialized to logic 1 by the host after reset). The
device asserts this bit when it recognizes ping-pong is active for this mode
code. Before loading the transmit data buffer for this mode code, the host can
ask the device to temporarily disable ping-pong by asserting STOPP bit 3.
The device acknowledges ping-pong is disabled by negating PPON. The host
can safely load or off-load the buffer without data collision while PPON is ne-
gated. After buffer servicing, the host asks the device to re-enable ping-pong
by negating STOPP bit 3. The device acknowledges ping-pong is re-enabled
by asserting PPON.
If PPEN bit 2 is asserted and PPON bit 8 is negated when a new command
arrives for this mode code, ping-pong disable handshake is in effect: The
device applies single-buffer index mode using Data Pointer A or Data Pointer
B, per DPB bit 10. The DPB bit does not toggle after command completion.
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
180