hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 173

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

19.5.2. Transmit Subaddress Control Word
Transmit Subaddress Control Words apply when a valid command word T/R bit equals one (transmit) and the subad-
dress field has a value in the range of 1 to 30 (0x1E). The descriptor Control Word defines terminal command response
and interrupt behavior, and conveys activity status to the host. It is initialized by the host before terminal execution
begins. Bits 8-11 cannot be written by the host; these bits are updated by the device during terminal execution, that is,
when Configuration Register 1 STEX bit equals 1. The host can write bits 0-2 and 4-7 only when STEX equals zero;
bits 3,12 and 14-15 can be written anytime. This register is cleared to 0x0000 by MR master reset. Software reset
(SRST) clears just the DBAC, DPB and BCAST bits. Following any host read cycle to the Control Word address,
the DBAC bit is reset.
NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is un-
changed unless specifically indicated by an “SR” value.
Bit No. Mnemonic R/W
MSB
15
14
13
12
15 14 13 12 11 10 9
H
IXEQZ
IWA
-----
MKBUSY
H
X
H
D1 D
D
Reset
D
8
0
0
0
0
H
7
H
6
Function
Interrupt When Index Equals Zero.
If the Interrupt Enable Register IXEQZ bit is high, assertion of this bit enables
generation of an interrupt for (a) subaddresses using indexed buffer mode
when the INDX value decrements from 1 to 0, or (b) subaddresses using a
circular buffer mode when the pre-determined number of messages has been
transacted. If enabled, upon completion of command processing that results
in index = 0, an IXEQZ interrupt is entered in the Pending Interrupt Register,
output pin INTMES is asserted, and the interrupt is registered in the Interrupt
Log.
Interrupt When Accessed.
If the Interrupt Enable Register IWA bit is high, assertion of this bit enables
interrupt generation when the subaddress receives any valid transmit com-
mand. If enabled, upon completion of command processing, an IWA interrupt
is entered in the Pending Interrupt Register, output pin INTMES is asserted,
and the interrupt is registered in the Interrupt Log.
Not Used
Make Busy.
The host asserts the MKBUSY bit to respond with Busy status for commands
to this transmit subaddress. This bit is an alternative to globally applying Busy
status for all valid commands, enabled from the 1553 Status Bits Register.
See that register description for additional information. When Busy is as-
serted, data words are not transmitted and the DPB bit does not toggle after
message completion.
H
5
HOLT INTEGRATED CIRCUITS
H
4
HI-6130, HI-6131
H
3
H
2
H
1
H
0
173
LSB
D1
H
D
X
Bit maintained by host
Bit maintained by device
Bit set by device, reset by host read cycle
Bit is not used, may be logic 0 or 1