hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 196

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

must be processed before another broadcast message
arrives to prevent loss of data. Broadcast messages do
not decrement the INDX register, and Data Pointer A is
not updated in message post-processing. This scheme
may be well suited for Single Message Mode (INDX = 0)
when the host can reliably service either the broadcast
data buffer or data buffer A before the next receive mes-
sage arrives for the same subaddress (or mode code).
Option 1 Setup: At initialization, host asserts NOTICE2
bit in Configuration Register 1 and sets the Control Word
IBR (Interrupt Broadcast Received) bit for each index
mode descriptor block. The IBR bit is also asserted in
the Interrupt Enable Register.
When a broadcast command is received, message in-
formation and data are stored in the broadcast data buf-
fer. If descriptor Control Word IBR bit is set, an INTMES
interrupt is generated. The host must read the Interrupt
Log to determine the originating subaddress (or mode
code) then service the broadcast data buffer for that
subaddress (or mode code) before the next broadcast
message to the same subaddress (or mode code) ar-
rives.
Option 2 for Index Mode Broadcast Messages:
The second alternative stores both broadcast and non-
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
196
broadcast message information in data buffer A. Op-
tional IBR interrupts can signal arrival of broadcast
messages. The RT handles broadcast messages just
like non-broadcast messages, except the Message In-
formation Word BCAST bit is asserted to identify broad-
cast messages during host buffer servicing. All mes-
sages decrement the INDX register and Data Pointer A
is updated in message post-processing. This scheme is
compatible with Single Message Mode or conventional
N-message indexing. For Notice II compliance, separa-
tion of broadcast and non-broadcast data occurs within
the host.
Option 2 Setup: At initialization, host negates the
NOTICE2 bit in Configuration Register 1. If broadcast
interrupts are used, the Control Word IBR (Interrupt
Broadcast Received) bit is asserted at each desired
index mode descriptor block. The IBR bit is also asserted
in the Interrupt Enable Register.
Using option 2, the host has several options for servicing
data buffer A: (a) when INDX decrements from one to
zero (using the IXEQZ interrupt), (b) when a broadcast
message occurs (using the IBR interrupt) or (c) when
any message arrives (using the IWA interrupt).